proj.fit.qmsg

LCD1602显示源代码 1。源文件保存在src目录

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 07 23:45:56 2008 " "Info: Processing started: Mon Apr 07 23:45:56 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off LCD_Test -c Proj " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LCD_Test -c Proj" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Proj EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"Proj\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 153 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 153" {  } { { "lcd_test.bdf" "" { Schematic "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcd:inst\|clk_int Global clock " "Info: Automatically promoted some destinations of signal \"lcd:inst\|clk_int\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:inst\|clk_int " "Info: Destination \"lcd:inst\|clk_int\" may be non-global or may not use global clock" {  } { { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 72 -1 0 } }  } 0}  } { { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 72 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "div16:inst1\|count\[3\] Global clock " "Info: Automatically promoted some destinations of signal \"div16:inst1\|count\[3\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div16:inst1\|count\[3\] " "Info: Destination \"div16:inst1\|count\[3\]\" may be non-global or may not use global clock" {  } { { "../src/div16.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/div16.v" 5 -1 0 } }  } 0}  } { { "../src/div16.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/div16.v" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcd:inst\|clkdiv Global clock " "Info: Automatically promoted some destinations of signal \"lcd:inst\|clkdiv\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:inst\|clkdiv " "Info: Destination \"lcd:inst\|clkdiv\" may be non-global or may not use global clock" {  } { { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 76 -1 0 } }  } 0}  } { { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 76 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SYS_RST Global clock " "Info: Automatically promoted signal \"SYS_RST\" to use Global clock" {  } { { "lcd_test.bdf" "" { Schematic "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/lcd_test.bdf" { { 240 216 384 256 "SYS_RST" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "SYS_RST " "Info: Pin \"SYS_RST\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "lcd_test.bdf" "" { Schematic "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/lcd_test.bdf" { { 240 216 384 256 "SYS_RST" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SYS_RST" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "" { SYS_RST } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/Proj.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/Proj.fld" "" "" { SYS_RST } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.764 ns register register " "Info: Estimated most critical path is register to register delay of 5.764 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[4\] 1 REG LAB_X49_Y17 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X49_Y17; Fanout = 15; REG Node = 'lcd:inst\|counter\[4\]'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "" { lcd:inst|counter[4] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.169 ns) + CELL(0.292 ns) 1.461 ns lcd:inst\|LessThan~389 2 COMB LAB_X49_Y19 3 " "Info: 2: + IC(1.169 ns) + CELL(0.292 ns) = 1.461 ns; Loc. = LAB_X49_Y19; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~389'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.461 ns" { lcd:inst|counter[4] lcd:inst|LessThan~389 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(0.590 ns) 2.846 ns lcd:inst\|LessThan~391 3 COMB LAB_X49_Y17 3 " "Info: 3: + IC(0.795 ns) + CELL(0.590 ns) = 2.846 ns; Loc. = LAB_X49_Y17; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~391'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.385 ns" { lcd:inst|LessThan~389 lcd:inst|LessThan~391 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.442 ns) 4.212 ns lcd:inst\|char_addr~1496 4 COMB LAB_X50_Y18 3 " "Info: 4: + IC(0.924 ns) + CELL(0.442 ns) = 4.212 ns; Loc. = LAB_X50_Y18; Fanout = 3; COMB Node = 'lcd:inst\|char_addr~1496'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.366 ns" { lcd:inst|LessThan~391 lcd:inst|char_addr~1496 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.074 ns) + CELL(0.478 ns) 5.764 ns lcd:inst\|state\[9\] 5 REG LAB_X50_Y17 5 " "Info: 5: + IC(1.074 ns) + CELL(0.478 ns) = 5.764 ns; Loc. = LAB_X50_Y17; Fanout = 5; REG Node = 'lcd:inst\|state\[9\]'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.552 ns" { lcd:inst|char_addr~1496 lcd:inst|state[9] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns 31.26 % " "Info: Total cell delay = 1.802 ns ( 31.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.962 ns 68.74 % " "Info: Total interconnect delay = 3.962 ns ( 68.74 % )" {  } {  } 0}  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "5.764 ns" { lcd:inst|counter[4] lcd:inst|LessThan~389 lcd:inst|LessThan~391 lcd:inst|char_addr~1496 lcd:inst|state[9] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 07 23:46:07 2008 " "Info: Processing ended: Mon Apr 07 23:46:07 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}