nl_prsg9.vhd

vhdl的伪随机序列发射器程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED;

ENTITY NL_prsg9 IS
PORT(rst,clk : IN STD_LOGIC;
     Sel     : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     N_L_Sel : IN STD_LOGIC;
       dataout : OUT STD_LOGIC);
END NL_prsg9;

ARCHITECTURE sample OF NL_prsg9 IS
COMPONENT dff
PORT(d,clk: IN STD_LOGIC;
		  q : OUT STD_LOGIC);
END COMPONENT;

SIGNAL z: STD_LOGIC_VECTOR(8 downTO 0);
signal prn: std_logic;
BEGIN
lp: FOR i IN 0 to 7 GENERATE
	dffx: dff PORT MAP(d=>z(i),clk=>clk,q=>z(i+1));
	END GENERATE lp;
	
PROCESS(clk,rst)
BEGIN
	--if rst='1' then
	--   z<="000000000";
	-- els
	IF rising_edge(clk) THEN
	   IF z="000000000" THEN
			z(0)<='1';
		ELSE
	      z(0)<=z(8) XOR z(4)  XOR ((NOT z(7)) AND (NOT z(6)) AND (NOT z(5)) AND (NOT z(4)) AND (NOT z(3)) AND (NOT z(2)) AND (NOT z(1)) AND z(0)) XOR ((NOT z(7)) AND z(6) AND z(5) AND (NOT z(4)) AND z(3) AND (NOT z(2)) AND z(1) AND (NOT z(0)));
		END IF;
	END IF;
END PROCESS;
 	dataout<=z(8);
END sample;