speaker.txt

梁祝乐曲演奏电路设计

library ieee;
use ieee.std_logic_1164.all;
entity speakera1 is
    port(clk:in std_logic;
        tone:in integer range 0 to 16#7FF#;
        spks:out std_logic);
end ;
architecture one of speakera1 is
  signal preclk :std_logic;
  signal fullspks:std_logic;
begin
  divideclk:process(clk)
variable count4:integer range 0 to 15;
begin
   preclk<='0';
   if count4>11 then preclk<='1';count4:=0;
elsif clk'event and clk='1'then count4:=count4+1;
end if;
end process;
genspks:process(preclk,tone)
    variable count11:integer range 0 to 16#7FF#;
begin
     if preclk'event and preclk='1'then
      if count11=16#7FF# then
         count11:=tone;
         fullspks<='1';
      else count11:=count11+1;
         fullspks<='0';end if;
     end if;
end process;
delayspks:process(fullspks)
    variable count2:std_logic;
begin
  if fullspks'event and fullspks='1'then
        count2:=not count2;
     if count2='1'then spks<='1';
     else spks<='0';end if;
end if;
end process;
end;