reg8.txt

来自「梁祝乐曲演奏电路设计」· 文本 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
entity reg8_1 is 
  port (clk,ldn,clrn:in bit;
        dsr:in std_logic;
          d:in std_logic_vector(7 downto 0);
          q:out std_logic_vector(7 downto 0));
end reg8_1;
architecture one of reg8_1 is
   signal sreg8:std_logic_vector(7 downto 0);
begin
process(clrn,clk,ldn,d)
  begin 
    if clrn='0' then sreg8<="00000000";    else
      if clk'event and clk='1' then
        if ldn='0'then sreg8<=d;
          else sreg8( 6 downto 0)<=sreg8(7 downto 1);
               sreg8(7)<=dsr;
        end if;
      end if;
    end if;
    q<=sreg8;
  end process;
end one;