📄 aa.fit.rpt
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Fitter report for aa
Mon May 05 10:01:18 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Input Pins
7. Output Pins
8. All Package Pins
9. Non-Global High Fan-Out Signals
10. Local Routing Interconnect
11. MegaLAB Interconnect
12. LAB External Interconnect
13. MegaLAB Usage Summary
14. Row Interconnect
15. LAB Column Interconnect
16. ESB Column Interconnect
17. Fitter Resource Usage Summary
18. Fitter Resource Utilization by Entity
19. Delay Chain Summary
20. I/O Bank Usage
21. Pin-Out File
22. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Mon May 05 10:01:18 2008 ;
; Quartus II Version ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name ; aa ;
; Top-level Entity Name ; aa ;
; Family ; APEX20KE ;
; Device ; EP20K300EQC240-1 ;
; Timing Models ; Final ;
; Total logic elements ; 12 / 11,520 ( < 1 % ) ;
; Total pins ; 14 / 152 ( 9 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 147,456 ( 0 % ) ;
; Total PLLs ; 0 ;
+-----------------------+------------------------------------------+
+------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------+--------------------+--------------------+
; Device ; EP20K300EQC240-1 ; ;
; SignalProbe signals routed during normal compilation ; Off ; Off ;
; Use smart compilation ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Turbo Bit ; On ; On ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Auto Global Clock ; On ; On ;
; Auto Global Output Enable ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/add_4/aa.fit.eqn.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
; Name ; Pin # ; MegaLAB Row ; MegaLAB Col. ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; PCI I/O Enabled ; Single-Pin CE ; FastRow Interconnect ; I/O Standard ;
+------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
; cin ; 59 ; R ; -- ; -- ; 3 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; b[0] ; 118 ; -- ; 1 ; 3 ; 4 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; a[0] ; 58 ; R ; -- ; -- ; 4 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; b[1] ; 143 ; J ; -- ; -- ; 2 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; a[1] ; 130 ; O ; -- ; -- ; 2 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; b[2] ; 136 ; L ; -- ; -- ; 3 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; a[2] ; 138 ; K ; -- ; -- ; 4 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; b[3] ; 121 ; R ; -- ; -- ; 2 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; a[3] ; 113 ; -- ; 1 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
+------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+-----------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; Name ; Pin # ; MegaLAB Row ; MegaLAB Col. ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Single-Pin OE ; Single-Pin CE ; Open Drain ; TRI Primitive ; I/O Standard ;
+-----------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; bcdout[0] ; 109 ; -- ; 1 ; 15 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; bcdout[1] ; 110 ; -- ; 1 ; 14 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; bcdout[2] ; 114 ; -- ; 1 ; 9 ; no ; yes ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; bcdout[3] ; 116 ; -- ; 1 ; 6 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; cout ; 115 ; -- ; 1 ; 7 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
+-----------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
+-----------------------------------+
; All Package Pins ;
+-------+------------+--------------+
; Pin # ; Usage ; I/O Standard ;
+-------+------------+--------------+
; 1 ; VCC_INT ; ;
; 2 ; GND* ; ;
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