📄 aa.tan.rpt
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Timing Analyzer report for aa
Mon May 05 10:01:32 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 16.982 ns ; a[0] ; cout ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP20K300EQC240-1 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+----------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+-----------+
; N/A ; None ; 16.982 ns ; a[0] ; cout ;
; N/A ; None ; 16.544 ns ; a[0] ; bcdout[3] ;
; N/A ; None ; 16.506 ns ; cin ; cout ;
; N/A ; None ; 16.068 ns ; cin ; bcdout[3] ;
; N/A ; None ; 15.244 ns ; a[0] ; bcdout[2] ;
; N/A ; None ; 14.768 ns ; cin ; bcdout[2] ;
; N/A ; None ; 14.750 ns ; a[0] ; bcdout[1] ;
; N/A ; None ; 14.275 ns ; cin ; bcdout[1] ;
; N/A ; None ; 13.866 ns ; a[0] ; bcdout[0] ;
; N/A ; None ; 13.586 ns ; b[0] ; cout ;
; N/A ; None ; 13.396 ns ; cin ; bcdout[0] ;
; N/A ; None ; 13.148 ns ; b[0] ; bcdout[3] ;
; N/A ; None ; 12.753 ns ; b[1] ; cout ;
; N/A ; None ; 12.676 ns ; a[1] ; cout ;
; N/A ; None ; 12.315 ns ; b[1] ; bcdout[3] ;
; N/A ; None ; 12.238 ns ; a[1] ; bcdout[3] ;
; N/A ; None ; 11.848 ns ; b[0] ; bcdout[2] ;
; N/A ; None ; 11.837 ns ; a[2] ; cout ;
; N/A ; None ; 11.387 ns ; a[2] ; bcdout[3] ;
; N/A ; None ; 11.364 ns ; b[2] ; cout ;
; N/A ; None ; 11.354 ns ; b[0] ; bcdout[1] ;
; N/A ; None ; 11.015 ns ; b[1] ; bcdout[2] ;
; N/A ; None ; 10.938 ns ; a[1] ; bcdout[2] ;
; N/A ; None ; 10.918 ns ; b[1] ; bcdout[1] ;
; N/A ; None ; 10.916 ns ; b[2] ; bcdout[3] ;
; N/A ; None ; 10.842 ns ; a[1] ; bcdout[1] ;
; N/A ; None ; 10.803 ns ; b[0] ; bcdout[0] ;
; N/A ; None ; 10.603 ns ; a[3] ; bcdout[3] ;
; N/A ; None ; 10.584 ns ; a[3] ; cout ;
; N/A ; None ; 10.099 ns ; a[2] ; bcdout[2] ;
; N/A ; None ; 10.070 ns ; b[3] ; cout ;
; N/A ; None ; 10.064 ns ; b[3] ; bcdout[3] ;
; N/A ; None ; 9.626 ns ; b[2] ; bcdout[2] ;
+-------+-------------------+-----------------+------+-----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon May 05 10:01:30 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off aa -c aa
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a[0]" to destination pin "cout" is 16.982 ns
Info: 1: + IC(0.000 ns) + CELL(1.840 ns) = 1.840 ns; Loc. = PIN_58; Fanout = 4; PIN Node = 'a[0]'
Info: 2: + IC(7.992 ns) + CELL(0.782 ns) = 10.614 ns; Loc. = LC5_8_R1; Fanout = 1; COMB Node = 'co[0]~150'
Info: 3: + IC(0.222 ns) + CELL(0.710 ns) = 11.546 ns; Loc. = LC6_8_R1; Fanout = 4; COMB Node = 'co[1]~151'
Info: 4: + IC(0.276 ns) + CELL(0.710 ns) = 12.532 ns; Loc. = LC9_9_R1; Fanout = 1; COMB Node = 'co[2]~154'
Info: 5: + IC(0.222 ns) + CELL(0.782 ns) = 13.536 ns; Loc. = LC9_8_R1; Fanout = 1; COMB Node = 'co~155'
Info: 6: + IC(0.956 ns) + CELL(2.490 ns) = 16.982 ns; Loc. = PIN_115; Fanout = 0; PIN Node = 'cout'
Info: Total cell delay = 7.314 ns ( 43.07 % )
Info: Total interconnect delay = 9.668 ns ( 56.93 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Mon May 05 10:01:32 2008
Info: Elapsed time: 00:00:03
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