const_mult.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY const_mult IS
    GENERIC (  N : INTEGER  :=  8;          --RGB信号宽度
               M : INTEGER  := 8;           --系数宽度
              CST_MULT : INTEGER  := 66     --常数乘数
            );
    PORT ( Clock       : IN  STD_LOGIC;     --时钟
           ClockEnable : IN  STD_LOGIC;     --时钟使能
           Reset       : IN  STD_LOGIC;     --复位
           Color       : IN  STD_LOGIC_VECTOR( N-1 DOWNTO 0);   --输入变量乘数
           Color_Out   : OUT STD_LOGIC_VECTOR(N+M-1 DOWNTO 0)   --乘法器输出
	   );
END const_mult;
ARCHITECTURE RTL OF const_mult IS
CONSTANT OUT_SIZE : INTEGER := N+M;                             --乘法器输出宽度
BEGIN
COLOR_KCM: PROCESS (Clock, Reset)
BEGIN
  IF (Reset = '1') THEN                                         --复位操作
    Color_Out <= (OTHERS => '0');
  ELSIF (Clock'event AND Clock = '1') THEN                      --乘法
    IF (ClockEnable = '1') THEN
		Color_Out <= CONV_STD_LOGIC_VECTOR( CONV_UNSIGNED(CST_MULT,M) * UNSIGNED(Color), OUT_SIZE) ;
	 END IF;
  END IF;
END PROCESS;
END RTL;