led_flicker.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY led_flicker IS
PORT(
		ena				: IN	STD_LOGIC_VECTOR(5 DOWNTO 0);         --位使能
		flicker_ena		: IN	STD_LOGIC_VECTOR(5 DOWNTO 0);         --位闪烁使能
		addr			: IN	STD_LOGIC_VECTOR(2 DOWNTO 0);         --当前显示LED管地址
		din				: IN	STD_LOGIC_VECTOR(6 DOWNTO 0);         --数据输入（a,b,c,d,e,f,g）
		dp  			: IN	STD_LOGIC;                            --小数点输入
		clk_flicker		: IN	STD_LOGIC;							  --闪烁时钟
		dout			: OUT   STD_LOGIC_VECTOR(6 DOWNTO 0);         --输出数据(a,b,c,d,e,f,g）
		dpout			: OUT   STD_LOGIC );                          --小数点输出
END led_flicker;
ARCHITECTURE rtl OF led_flicker IS
	--当前显示LED管的使能信号
	SIGNAL  ena_bit			: STD_LOGIC;
	--当前显示LED管的闪烁使能信号
	SIGNAL  flicker_ena_bit : STD_LOGIC;
BEGIN
	--多路选通器,给出当前显示LED管的使能信号和当前显示LED管的闪烁使能信号
	PROCESS(ena,flicker_ena,addr)
	BEGIN
		CASE addr IS
			WHEN "000" => 	ena_bit <= ena(0);
							flicker_ena_bit <= flicker_ena(0);
			WHEN "001" =>   ena_bit <= ena(1);
							flicker_ena_bit <= flicker_ena(1);
			WHEN "010" =>   ena_bit <= ena(2);
							flicker_ena_bit <= flicker_ena(2);
			WHEN "011" =>   ena_bit <= ena(3);
							flicker_ena_bit <= flicker_ena(3);
			WHEN "100" =>   ena_bit <= ena(4);
							flicker_ena_bit <= flicker_ena(4);
			WHEN "101" =>   ena_bit <= ena(5);
							flicker_ena_bit <= flicker_ena(5);
			WHEN OTHERS => ena_bit <= '0';
						   flicker_ena_bit <= '0';
		END CASE;
	END PROCESS;
	--输出模块
	PROCESS(ena_bit,flicker_ena_bit,din,dp,clk_flicker)
	BEGIN
		IF(ena_bit = '1') THEN
			IF(flicker_ena_bit='1') THEN
				--闪烁
				IF(clk_flicker='1')THEN
					dout <= din;
					dpout <= dp;
				ELSE
					dout <= "0000000";
					dpout <= '0';
				END IF;
			ELSE
				--不闪烁
				dout <= din;
				dpout <= dp;
			END IF;
		ELSE
			--输出不使能
			dout <= "0000000";
			dpout <= '0';
		END IF;
	END PROCESS;
END rtl;