disp_buf.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY disp_buf IS
PORT(
		clk			: IN	STD_LOGIC;                       --全局时钟
		ld			: IN	STD_LOGIC;                       --同步加载使能
		data		: IN    STD_LOGIC_VECTOR(29 DOWNTO 0);   --并行加载数据
		addr		: IN    STD_LOGIC_VECTOR(2 DOWNTO 0);    --地址输入
		sdata       : IN    STD_LOGIC_VECTOR(4 DOWNTO 0);    --串行加载数据
		wr			: IN    STD_LOGIC;						 --写信号
		dataout     : OUT	STD_LOGIC_VECTOR(29 DOWNTO 0));  --输出数据
END disp_buf;
ARCHITECTURE rtl OF disp_buf IS
BEGIN
	--同步加载寄存器
	PROCESS(clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			--并行加载
			IF(ld = '1') THEN
				dataout <= data;
			ELSIF(wr='1') THEN
			--串行加载
				CASE addr IS
					WHEN "000" =>  dataout(4 DOWNTO 0) <= sdata;
					WHEN "001" =>  dataout(9 DOWNTO 5) <= sdata;
					WHEN "010" =>  dataout(14 DOWNTO 10) <= sdata;
					WHEN "011" =>  dataout(19 DOWNTO 15) <= sdata;
					WHEN "100" =>  dataout(24 DOWNTO 20) <= sdata;
					WHEN "101" =>  dataout(29 DOWNTO 25) <= sdata;
					WHEN OTHERS =>  dataout(4 DOWNTO 0) <= sdata;
				END CASE;
			END IF;			
		END IF;
	END PROCESS;
END rtl;