key.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 53 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY key IS
PORT(
		clk			: IN	STD_LOGIC;                       --全局时钟
		keyin		: IN 	STD_LOGIC_VECTOR(3 DOWNTO 0);
		keyvalue	: OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
		keypressed	: OUT   STD_LOGIC;
		functionkey	: OUT    STD_LOGIC;
		keydrv     	: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));   
END key;
ARCHITECTURE rtl OF key IS
	COMPONENT keysan                                        --键盘扫描模块
		PORT(
			clk_scan	: IN	STD_LOGIC;                       --扫描时钟，周期10MS
			keydrv     	: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0));   --输出扫描信号
	END COMPONENT;
	COMPONENT clk_gen                                      --时钟产生模块
		PORT(
				clk       	: IN	STD_LOGIC;                      --全局时钟
				clk_scan    : OUT	STD_LOGIC                       --扫描时钟
			);
	END COMPONENT;
	COMPONENT keydecoder_deb                               --键盘译码和按键标志产生模块
		PORT(
			keyin	  	: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);	--键盘输入
			keydrv	  	: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);   --扫描输出
			clk       	: IN	STD_LOGIC;                      --全局时钟
			clk_scan    : IN	STD_LOGIC;                      --扫描时钟
			keyvalue  	: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0);   --键值
			keypressed 	: OUT   STD_LOGIC;                      --有键被按下标志
			functionkey : OUT   STD_LOGIC                       --功能键标志
			);
	END COMPONENT;
	SIGNAL clk_scan     :  STD_LOGIC;
BEGIN
	keysan1: keysan 
		PORT MAP (clk_scan => clk_scan, 
		          keydrv => keydrv);
	clk_gen1: clk_gen 
		PORT MAP (clk => clk, 
		          clk_scan => clk_scan);
	keydecode:keydecoder_deb
	PORT MAP (keyin => keyin, 
		      keydrv => keydrv,
			  clk => clk,
			  clk_scan => clk_scan,
			  keyvalue => keyvalue,
			  keypressed => keypressed,
			  functionkey => functionkey);
END rtl;