led_clk_gen.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY led_clk_gen IS
PORT(
		clk       	: IN	STD_LOGIC;                      --全局时钟
		clk_scan    : BUFFER STD_LOGIC;                      --扫描时钟
		CLK_flicker : OUT	STD_LOGIC                       --闪烁时钟
);
END led_clk_gen;
ARCHITECTURE rtl OF led_clk_gen IS
--仿真用这个语句
SIGNAL cnt1		: INTEGER RANGE 0 TO 7;
SIGNAL cnt2		: INTEGER RANGE 0 TO 4;
--下载在芯片上时用这个语句
--SIGNAL cnt1		: INTEGER RANGE 0 TO 39999; 
--SIGNAL cnt2		: INTEGER RANGE 0 TO 149; 
BEGIN
	--计数模块1
	PROCESS(clk)
	BEGIN
		IF(clk'event and clk='1') THEN
			IF(cnt1=cnt1'high) THEN
				cnt1 <= 0;
			ELSE
				cnt1 <= cnt1 + 1;
			END IF;
		END IF;
	END PROCESS;
	--计数模块2
	PROCESS(clk_scan)
	BEGIN
		IF(clk_scan'event and clk_scan='1') THEN
			IF(cnt2=cnt2'high) THEN
				cnt2 <= 0;
			ELSE
				cnt2 <= cnt2 + 1;
			END IF;
		END IF;
	END PROCESS;
	--译码输出1
	PROCESS(cnt1,clk)
	BEGIN
		IF(clk'event and clk='1') THEN	--寄存器锁存输出，目的消毛刺
			IF cnt1 >= cnt1'high/2+1 THEN
				clk_scan <= '1';
			ELSE
				clk_scan <= '0';
			END IF;
		END IF;
	END PROCESS;
	--译码输出2
	PROCESS(cnt2,clk_scan)
	BEGIN
		IF(clk_scan'event and clk_scan='1') THEN	--寄存器锁存输出，目的消毛刺
			IF cnt2 >= cnt2'high/2+1 THEN
				clk_flicker <= '1';
			ELSE
				clk_flicker <= '0';
			END IF;
		END IF;
	END PROCESS;
END rtl;