ledscan.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ledscan IS
PORT(
		clk_scan	: IN	STD_LOGIC;                       --扫描时钟，周期300HZ
		ledaddr		: OUT	STD_LOGIC_VECTOR(2 DOWNTO 0);    --当前显示LED的地址，用于多路选通
		ledsel     	: OUT	STD_LOGIC_VECTOR(5 DOWNTO 0));   --输出扫描信号
END ledscan;
ARCHITECTURE rtl OF ledscan IS
SIGNAL cnt			: INTEGER RANGE 0 TO 5; 
BEGIN
	--计数器进程
	PROCESS(clk_scan)
	BEGIN
		IF(clk_scan'event AND clk_scan='1')THEN
			IF(cnt=cnt'high)THEN
				cnt <= 0;
			ELSE
				cnt <= cnt +1;
			END IF;
		END IF;
	END PROCESS;
	--当前显示的LED管地址
    ledaddr <= CONV_STD_LOGIC_VECTOR(cnt,3);
	--片选信号输出
	PROCESS(cnt)
	BEGIN
		CASE cnt IS
			WHEN 0 => ledsel <= "000001";
			WHEN 1 => ledsel <= "000010";
			WHEN 2 => ledsel <= "000100";
			WHEN 3 => ledsel <= "001000";
			WHEN 4 => ledsel <= "010000";
			WHEN 5 => ledsel <= "100000";
			WHEN OTHERS => ledsel <= "000001";
		END CASE;
	END PROCESS;
END rtl;