keysan.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 38 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY keysan IS
PORT(
		clk_scan	: IN	STD_LOGIC;                       --扫描时钟，周期10MS
		keydrv     	: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0));   --输出扫描信号
END keysan;
ARCHITECTURE behavier OF keysan IS
	CONSTANT s0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1110";	 --定义状态机编码
	CONSTANT s1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1101";
	CONSTANT s2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
	CONSTANT s3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";
	SIGNAL   present_state : STD_LOGIC_VECTOR(3 DOWNTO 0);	 --状态机现态
	SIGNAL   next_state : STD_LOGIC_VECTOR(3 DOWNTO 0);      --状态极次态
BEGIN
	--状态更新进程
	PROCESS(clk_scan)                                        															
	BEGIN
		IF(clk_scan'event and clk_scan='1') THEN
			present_state <= next_state;
		END IF;
	END PROCESS;
    --状态译码
	PROCESS(present_state)
	BEGIN
		CASE present_state IS
			WHEN s0 => next_state<=s1;
			WHEN s1 => next_state<=s2;
			WHEN s2 => next_state<=s3;
			WHEN s3 => next_state<=s0;
			--多余态处理
			WHEN OTHERS => next_state<=s0;
		END CASE;
	END PROCESS;
	--输出译码
	keydrv <= present_state;
END behavier;