clk_gen.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 41 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clk_gen IS
PORT(
		clk       	: IN	STD_LOGIC;                      --全局时钟
		clk_scan    : OUT	STD_LOGIC                       --扫描时钟
);
END clk_gen;
ARCHITECTURE rtl OF clk_gen IS
--仿真用这个语句
SIGNAL cnt		: INTEGER RANGE 0 TO 199;
--下载在芯片上时用这个语句
--SIGNAL cnt		: INTEGER RANGE 0 TO 119999; 
BEGIN
	--计数模块
	PROCESS(clk)
	BEGIN
		IF(clk'event and clk='1') THEN
			IF(cnt=cnt'high) THEN
				cnt <= 0;
			ELSE
				cnt <= cnt+1;
			END IF;
		END IF;
	END PROCESS;
	--译码输出
	PROCESS(cnt,clk)
	BEGIN
		IF(clk'event and clk='1') THEN	--寄存器锁存输出，目的消毛刺
			IF cnt >= cnt'high/2 THEN
				clk_scan <= '1';
			ELSE
				clk_scan <= '0';
			END IF;
		END IF;
	END PROCESS;
END rtl;