radixpoint_gen.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 48 行

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY radixpoint_gen IS
	PORT(class          	 : IN INTEGER RANGE 0 TO 7;           --量程编号
		 mode     			 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);   --测量模式
		 dp					 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --小数点控制
END radixpoint_gen;
ARCHITECTURE rtl OF radixpoint_gen IS
BEGIN
	PROCESS(class,mode)
	BEGIN
		IF(mode="00")THEN
		--周期显示方式
			CASE class IS
				WHEN 0 => dp <= "0000001";
				WHEN 1 => dp <= "0000010";
				WHEN 2 => dp <= "0000100";
				WHEN 3 => dp <= "0001000";
				WHEN 4 => dp <= "0010000";
				WHEN 5 => dp <= "0100000";
				WHEN 6 => dp <= "1000000";
				WHEN 7 => dp <= "1111111";
				WHEN OTHERS => dp <= "0000000";
			END CASE;
		ELSIF(mode="01")THEN
		--频率显示方式
			CASE class IS
				WHEN 0 => dp <= "1111111";
				WHEN 1 => dp <= "1000000";
				WHEN 2 => dp <= "0100000";
				WHEN 3 => dp <= "0010000";
				WHEN 4 => dp <= "0001000";
				WHEN 5 => dp <= "0000100";
				WHEN 6 => dp <= "0000010";
				WHEN 7 => dp <= "0000001";
				WHEN OTHERS => dp <= "0000000";
			END CASE;
		ELSIF(mode="10")THEN
		--脉冲宽度显示方式
			dp <= "0000010";
		ELSE
		--未定义的显示方式
			dp <= "0000000";			
		END IF;	
	END PROCESS;
END rtl;