counter_bcd7_down.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter_bcd7_down IS
	PORT(clr,ena,clk          	 : IN STD_LOGIC;   --clr计数器清零，en计数使能，clk时钟
         preset					 : IN STD_LOGIC;   --预置数
		 q      				 : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);--计数器输出
		 zero	 			     : OUT STD_LOGIC ); --计数器的值为0
END counter_bcd7_down;
ARCHITECTURE rtl OF counter_bcd7_down IS
	--内部计数器
	SIGNAL q_sig	: STD_LOGIC_VECTOR(27 DOWNTO 0);
BEGIN
	PROCESS(clk,clr)
	BEGIN
		IF clr='1' THEN						  --异步清零
			q_sig <= (OTHERS => '0');
			zero <= '1';
		ELSIF(preset='1')THEN
			--实际使用这两个语句
			q_sig(27 DOWNTO 24) <= "0001";
			q_sig(23 DOWNTO 0) <= "000000000000000000000000";
			--仿真用这两个语句
			--q_sig(27 DOWNTO 24) <= "0000";
			--q_sig(23 DOWNTO 0) <= "000000000000000100000000";
			zero <= '0';
		ELSE
			IF clk='1' and clk'event THEN     --时钟上升沿
				IF ena='1' THEN				  
					IF(q_sig(3 DOWNTO 0) = "0000") THEN		  --计数使能时，且计数值为0时，计数器值变为9
						q_sig(3 DOWNTO 0) <= "1001";
						IF(q_sig(7 DOWNTO 4) = "0000") THEN
							q_sig(7 DOWNTO 4) <= "1001";
							IF(q_sig(11 DOWNTO 8) = "0000") THEN
								q_sig(11 DOWNTO 8) <= "1001";
								IF(q_sig(15 DOWNTO 12) = "0000") THEN
									q_sig(15 DOWNTO 12) <= "1001";
									IF(q_sig(19 DOWNTO 16) = "0000") THEN
										q_sig(19 DOWNTO 16) <= "1001";
										IF(q_sig(23 DOWNTO 20) = "0000") THEN
											q_sig(23 DOWNTO 20) <= "1001";
											IF(q_sig(27 DOWNTO 24) = "0000") THEN
												q_sig(27 DOWNTO 24) <= "1001";
											ELSE
												q_sig(27 DOWNTO 24) <= q_sig(27 DOWNTO 24) - 1;
											END IF;
										ELSE
											q_sig(23 DOWNTO 20) <= q_sig(23 DOWNTO 20) - 1;
										END IF;
									ELSE
										q_sig(19 DOWNTO 16) <= q_sig(19 DOWNTO 16) - 1;
									END IF;
								ELSE
									q_sig(15 DOWNTO 12) <= q_sig(15 DOWNTO 12) - 1;
								END IF;
								--******************************************************
							ELSE
								q_sig(11 DOWNTO 8) <= q_sig(11 DOWNTO 8) - 1;
							END IF;
						ELSE
							q_sig(7 DOWNTO 4) <= q_sig(7 DOWNTO 4) - 1;
						END IF;
					ELSE
						q_sig(3 DOWNTO 0) <= q_sig(3 DOWNTO 0) - 1;
					END IF;
				END IF;
				--计数值为0标志
				IF q_sig = CONV_STD_LOGIC_VECTOR(1,28) AND ena='1' THEN
					zero <= '1';
				ELSE
					zero <= '0';
				END IF;
			END IF;							 
		END IF;
	END PROCESS;
	q <= q_sig;
END rtl;