subtracter_bcd1.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 35 行

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY subtracter_bcd1 IS
PORT(--                    c = a-b-cin
	   a 		: IN STD_LOGIC_VECTOR(3 DOWNTO 0);       --被减数
	   b 		: IN STD_LOGIC_VECTOR(3 DOWNTO 0);       --减数
	   cin      : IN STD_LOGIC;                          --借位输入
	   c   		: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);      --差
	   cout		: OUT STD_LOGIC);	                     --借位输出 
END subtracter_bcd1;
ARCHITECTURE rtl OF subtracter_bcd1 IS
	SIGNAL c_temp  		:STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL cout_temp   	:STD_LOGIC;
	SIGNAL result_temp  :STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
	--二进制减法
	result_temp <= ('0' & a) - ('0' & b) - cin ;
	cout_temp <= result_temp(4);
	c_temp <= result_temp(3 DOWNTO 0);
    --bcd调整
	PROCESS(c_temp,cout_temp)
	BEGIN
		IF(cout_temp = '1')THEN
		--有借位时减6
			c <= c_temp - "0110";
		ELSE
		--无借位时，差等于二进制减法的差
			c <= c_temp;
		END IF;
	END PROCESS;
	cout <= cout_temp; 
END RTL;