fifo8_8.vhd

这是一些经典的vhdl example

Library Ieee;
Use Ieee.Std_Logic_1164.All;
Use Ieee.Std_Logic_ARITH.All;
USE Ieee.Std_Logic_UNSIGNED.All;
Entity Fifo8_8 Is
   Generic(M: Positive := 8;
           N: Positive := 8); 
   Port( Reset,Wrreq,Rdreq,Clock : In Std_Logic;
         Datain : In Std_Logic_Vector((N-1) Downto 0);
         Dataout : Out Std_Logic_Vector((N-1) Downto 0);
         Full, Empty : buffer Std_Logic);
End Fifo8_8;
Architecture Rtl Of Fifo8_8 Is
   Type Fifo_Array Is Array(0 To (M-1)) Of Bit_Vector((N-1) Downto 0);
   Signal Fifo_Memory : Fifo_Array;
   Signal Wraddr, Rdaddr, Offset : Natural Range 0 To (M-1);
   Signal Rdpulse,Wrpulse, Q1, Q2, Q3, Q4 : Std_Logic;
   Signal Databuffer : Bit_Vector((N-1) Downto 0);
   --Signal Z :Std_Logic_Vector((N-1) Downto 0);
Begin
	Process(Clock)
    Begin
        If Clock'event And Clock='1' Then
             Q1 <= Wrreq;
             Q2 <= Q1;
             Q3 <= Rdreq;
             Q4 <= Q3;
		End If;
	End Process;
	Wrpulse <= Q1 And Not(Q2);
	Rdpulse <= Q3 And Not(Q4);
Fifo_Read : Process(Clock)
   Begin
      If Clock'event And Clock='1' Then
	      If Reset = '1' Then
	         Rdaddr <= 0;
	         Databuffer <= (Others => '0');
	      Elsif (Rdpulse = '1' And Empty = '0') Then
	         Databuffer <= Fifo_Memory(Rdaddr);
			 If Rdaddr/=Rdaddr'high Then
	         	Rdaddr <= Rdaddr + 1;
			 Else
				Rdaddr <= 0;
			End If;
	      End If;
	  End If;
   End Process;
Fifo_Write : Process(Clock,reset,wrpulse,datain)
   Begin
      If Clock'event And Clock='1' Then
	      If Reset = '1' Then
	         Wraddr <= 0;
	      Elsif (Wrpulse = '1' And Full = '0') Then
	         --Fifo_Memory(Wraddr) <= To_Bitvector(Datain);
			 case Wraddr IS
				when 0 => Fifo_Memory(0) <= To_Bitvector(Datain);
				when 1 => Fifo_Memory(1) <= To_Bitvector(Datain);
				when 2 => Fifo_Memory(2) <= To_Bitvector(Datain);
				when 3 => Fifo_Memory(3) <= To_Bitvector(Datain);
				when 4 => Fifo_Memory(4) <= To_Bitvector(Datain);
				when 5 => Fifo_Memory(5) <= To_Bitvector(Datain);
				when 6 => Fifo_Memory(6) <= To_Bitvector(Datain);
				when 7 => Fifo_Memory(7) <= To_Bitvector(Datain);
				when others => null;
			 end case;
	         If Wraddr >= Wraddr'high Then
	         	Wraddr <= 0;
			 Else
				Wraddr <= Wraddr + 1;
			End If;
		 End If;
	  End If;
   End Process;
Fifo_Offset:Process(Wraddr,Rdaddr)
	Begin
		If(Wraddr > Rdaddr) Then
			Offset <= (Wraddr - Rdaddr);
		Elsif(Rdaddr > Wraddr) Then
            Offset <=(M - (Rdaddr - Wraddr));
        Else
			Offset <=0;
		End If;
	End Process;
Fifo_Fm:Process(Offset)
	Begin
		If Offset = offset'low Then
			Empty <= '1';
			Full <= '0';
		Elsif Offset = offset'high Then
			Empty <= '0';
			Full <= '1';
		Else
			Empty <= '0';
			Full <= '0';
		End If;
	End Process;
Fifodut:Process(Rdreq,Databuffer)
	Begin
		If Rdpulse = '0' Then
			Dataout <= To_Stdlogicvector(Databuffer);
		Else
			Dataout <= "ZZZZZZZZ";
		End If;
    End Process;
End Rtl;