ram_dp_64_2.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 41 行

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ram_dp_64_2 IS 
	PORT(
	        wr_ad   	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);     --写地址信号
             rd_ad      : IN STD_LOGIC_VECTOR (5 DOWNTO 0);     --读地址信号
	        wr_clk 	: IN STD_LOGIC;                            --写时钟
             rd_clk 	: IN STD_LOGIC;                            --读时钟
	        din     	: IN STD_LOGIC_VECTOR(1 DOWNTO 0);      --写数据总线
            dout        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);    --读数据总线
	       wr_en	: IN STD_LOGIC  := '0';                       --读使能信号
	       rd_en	: IN STD_LOGIC  := '0'                       --写使能信号
      	); 
END ram_dp_64_2; 
ARCHITECTURE rtl OF ram_dp_64_2 IS 
	SUBTYPE ram_word IS STD_LOGIC_VECTOR (1 DOWNTO 0);   --定义一个存储单元的内容
	TYPE ram_table IS ARRAY (0 TO 63) OF ram_word;      --定义存储器有256个存储单元
	SIGNAL ram: ram_table; 
BEGIN 
 	PROCESS(wr_clk) 
	--写操作
 	BEGIN 
		IF wr_clk'EVENT AND wr_clk = '1' THEN
			IF wr_en='1' THEN
				 ram(CONV_INTEGER(wr_ad)) <= din;	
			END IF;
		END IF; 
	END PROCESS;
	PROCESS(rd_clk) 
	--读操作
	BEGIN 
		IF rd_clk'EVENT AND rd_clk = '1' THEN
			IF rd_en='1' THEN
			 	dout <= ram(CONV_INTEGER(rd_ad)); 
			END IF;
		END IF; 
	END PROCESS; 
END rtl;