mseq_struct.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY mseq_struct IS
   GENERIC(x : INTEGER := 3);      --寄存器宽度
   PORt(
        --clk时钟
      	clk     : IN STD_LOGIC;
		q       : OUT STD_LOGIC_VECTOR(x-1 DOWNTO 0)      --q序列输出
   );
END mseq_struct;
ARCHITECTURE rtl OF mseq_struct IS
   SIGNAL reg  : STD_LOGIC_VECTOR(x-1 DOWNTO 0);
   SIGNAL zero : STD_LOGIC_VECTOR(x-1 DOWNTO 0);          --宽度为x的全零信号
BEGIN
   PROCESS(clk)
   BEGIN
	  IF clk'event AND clk = '1' THEN 
		 IF reg=zero THEN 
			--自启动功能
		 	reg(0)<='1'; 
			reg(x-1 DOWNTO 1)<=zero(x-1 DOWNTO 1);
         ELSE 	
			--M序列产生
			reg<=(reg(0) XOR reg(1)) & reg(x-1 DOWNTO 1);
	 	 END IF;
     END IF;
   END PROCESS;
   --输出
   q<=reg;
   g1:FOR i IN x-1 DOWNTO 0 GENERATE
	zero(i)<='0';
	END GENERATE;
END rtl;