or2.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY or2 IS
PORT(
		a,b		: IN	STD_LOGIC;
		y	    : OUT	STD_LOGIC);
END or2;
ARCHITECTURE behavier OF or2 IS
BEGIN
	y<=a OR b;
END behavier;