and8_use_and2_test.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and8_use_and2_test IS
PORT(
		a1,a2,a3,a4,a5,a6,a7,a8		: IN	STD_LOGIC;
		y   	    				: OUT	STD_LOGIC);
END and8_use_and2_test;
ARCHITECTURE behavier OF and8_use_and2_test IS
	COMPONENT myand2              --2 输入与门元件声明
		PORT(
		a,b		: IN	STD_LOGIC;
		y       : OUT	STD_LOGIC);
	END COMPONENT;
signal a_in			: STD_LOGIC_VECTOR(7 downto 0);
signal temp			: STD_LOGIC_VECTOR(8 downto 0);
BEGIN
	a_in<=a8&a7&a6&a5&a4&a3&a2&a1;	--输入的数组形式
    temp(0)<='1';
	g1: FOR i IN 0 to 7 GENERATE                  --2 输入与门元件声明例化
       and2_portmap: myand2 PORT MAP(a=>a_in(i),                                     
									 b=>temp(i),
                                     y=>temp(i+1));
        END GENERATE; 
    y <=temp(8);	
END behavier;