decoder7.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY decoder7 IS
		PORT(
		bcd	    : IN	STD_LOGIC_VECTOR(3 downto 0);   --二—进制输入
		dout	: OUT	STD_LOGIC_vector(6 downto 0));  --译码输出
END decoder7;
ARCHITECTURE rtl OF decoder7 IS
BEGIN
process(bcd)
begin
	case bcd is
          when B"0000" => dout<=B"0111111";
          when B"0001" => dout<=B"0000110";
 		  when B"0010" => dout<=B"1011011";
		  when B"0011" => dout<=B"1001111";
		  when B"0100" => dout<=B"1100110";
		  when B"0101" => dout<=B"1101101";
		  when B"0110" => dout<=B"1111101";
		  when B"0111" => dout<=B"0000111";
		  when B"1000" => dout<=B"1111111";
		  when B"1001" => dout<=B"1101111";
		  when others  => dout<="0000000";   --其余时候熄灯
   end case;
end process;
END rtl;