bidir_bus.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bidir_bus IS
    PORT(
        a,b   : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);     --数据,宽度8位
        en    : IN STD_LOGIC;                            --输出使能
        dr    : IN STD_LOGIC);                           --数据流动方向
END bidir_bus;
ARCHITECTURE behavier OF bidir_bus IS
BEGIN                                        
    PROCESS(a,b,en,dr)
    BEGIN
	    IF en='1' AND dr='1' THEN  
	        b <= a; ;
		ELSIF en='1' AND dr='0' THEN      
			a <= b;            
	    ELSIF en='0' AND dr='1' THEN                    --输出使能为无