tri_gate.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_gate is PORT(
        d,en:     IN STD_LOGIC;		--d为输数据,en为输入控制信号
       q:         OUT STD_LOGIC);	--输出信号
END tri_gate;

ARCHITECTURE behavier OF tri_gate IS
BEGIN
	PROCESS(d,en)
   	BEGIN
         IF en = '0' THEN
               q<='Z';
         ELSE
               q <= d;
         END IF;
   END PROCESS;
END behavier;