stemdetecor_mealy.vhd

这是一些经典的vhdl example

LIBRARY IEEE; 
USE ieee.std_logic_1164.all ;
ENTITY StemDetecor_mealy IS
	PORT(
		clk								: IN	STD_LOGIC;    --状态机时钟
		reset								: IN	STD_LOGIC;    --异步复位
		din								: IN	STD_LOGIC;    --数据输入
		dout								: OUT	STD_LOGIC);   --检测结果输出
END StemDetecor_mealy;

ARCHITECTURE behavier OF StemDetecor_mealy IS
	TYPE STATE_TYPE IS (A,B);
	SIGNAL present_state: STATE_TYPE;
	SIGNAL next_state: STATE_TYPE;
BEGIN
	update :PROCESS(reset, clk)			    --每个时钟上升沿，更新状态
     BEGIN
   	     IF (reset = '1') THEN 					--状态机复位
	 		present_state <= A;
	     ELSIF (clk'EVENT AND clk='1') THEN     --状态更新
	 		present_state <= next_state;
	     END IF;
    END PROCESS update;

	statedecoder:PROCESS(clk)					--状态译码
	BEGIN
		CASE present_state IS
			WHEN A =>
				IF din='1' THEN
					next_state <= B;
				ELSE
					next_state <= A;
				END IF;
			WHEN B =>
				IF din='0' THEN
					next_state <= A;
				ELSE
					next_state <= B;
				END IF;
		END CASE;
	END PROCESS statedecoder;

	outputdecoder:PROCESS(clk,present_state,din)      --输出译码
	BEGIN	
		IF reset='1' THEN
			dout<='0';
		ELSE
			IF clk'EVENT AND clk = '1' THEN				   --同步输出
				IF present_state = B and din = '1' THEN
					dout<='1';
				ELSE
					dout<='0';
				END IF;	
			END IF;
	    END IF;
	END PROCESS outputdecoder;
END behavier;