statemachine_mealy.vhd

这是一些经典的vhdl example

--莫尔机的一般VHDL描述 
LIBRARY ieee; 
USE ieee.std_logic_1164.all ;

ENTITY statemachine_moore IS
  PORT(
     clock            : IN    STD_LOGIC;       --clock状态机时钟              
     reset            : IN    STD_LOGIC;	   --状态机复位	  
     input_one        : IN    STD_LOGIC; 	   --状态机输入
     input_two        : IN    STD_LOGIC;
      :
     etc. 
                        
     output_one       : OUT   STD_LOGIC;   	   --状态机输出
     output_two       : OUT   STD_LOGIC;
      : 
     etc.             : OUT   STD_LOGIC);                    
END statemachine_moore;                          

ARCHITECTURE example OF state_machine_moore IS
TYPE state IS (idle, first, second, .... etc.); --定义状态机状态
SIGNAL present_state, next_state : state;       --定义当前状态和下一状态
BEGIN
     update : PROCESS (reset, clock)			--每个时钟上升沿，更新状态
     BEGIN
   	     IF (reset = '1') THEN 					--状态机复位
	 		present_state <= idle;
	     ELSIF (clock'EVENT AND clock='1') THEN --状态更新
	 		present_state <= next_state;
	     END IF;
    END PROCESS update;

    sequencer : PROCESS (present_state, input_one, intput_two,... etc.)  --状态译码
    BEGIN
      	 CASE present_state IS
             WHEN idle =>                                          
    			IF (event_one = '1') THEN
					next_state <= first;
				ELSIF (event_two = '1'; THEN
					next_state <= .....;
				ELSIF .......
		  			........;	
		  			etc.
				END IF;
            WHEN first =>                                          
 				IF (event_.... = '1') THEN
					next_state <= ..... ;
				ELSIF ...... etc. 
				END IF;			                  
                next_state <= .... ;
            WHEN second =>
                  ..... etc.
	END CASE;
    END PROCESS sequencer;

	output:PROCESS(present_state,clk)      --输出译码
	BEGIN			
		IF clock='1' AND clock'event THEN		--输出同步
			output_one=FUNC(present_state); 	--输出仅决定于状态还决定于输入
			output_two=FUNC(present_state);
			... etc.
		END IF;
	END PROCESS;
END example;