and2.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and2 IS
PORT(
		aa,bb		: IN	STD_LOGIC;
		yy      : OUT	STD_LOGIC);
END and2;
ARCHITECTURE behavier OF and2 IS
BEGIN
	yy<=aa AND bb;
END behavier;