rs_latch.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all ;
ENTITY rs_latch IS
	PORT(enable,r,s  	: IN STD_LOGIC;   --ena输入使能，data输入数据
		 q,q_bar		: OUT STD_LOGIC); --锁存器输出
END rs_latch;
ARCHITECTURE rtl OF rs_latch IS
BEGIN
	PROCESS(enable,r,s)
	BEGIN
		IF enable = '1' and r = '1' and s = '0' THEN		 --复位操作
			q_bar <= '1';
			q     <= '0';
		ELSIF enable = '1' and r = '0' and s= '1' THEN       --置位操作
			q_bar <='0';
			q <= '1';
		ELSIF enable = '1' and r = '1' and s = '1' THEN    --在rs锁存器中不允许出现的情况
			q_bar <= '0';
			q     <= '0';
		END IF;										 --其他情况默认保持输出不变
	END PROCESS;
END rtl;