encoder8_3.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY encoder8_3 IS
PORT(
		D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --输入待编码信号
        A : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); --编码输出
END encoder8_3;
ARCHITECTURE behavier OF encoder8_3 IS
BEGIN
	PROCESS(D)
        BEGIN
                IF D(7) = '0' THEN
                        A <= "000";
                ELSIF D(6) = '0' THEN
                        A <= "001";
                ELSIF D(5) = '1' THEN
                        A <= "010";
                ELSIF D(4) = '1' THEN
                        A <= "011";
                ELSIF D(3) = '1' THEN
                        A <= "100";
                ELSIF D(2) = '1' THEN
                        A <= "101";
                ELSIF D(1) = '1' THEN
                        A <= "110";
                ELSIF D(0) = '1' THEN
                        A <= "111";
				ELSE
						A<="ZZZ";
                END IF;
END PROCESS;    
END behavier;