d_latch.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all ;
ENTITY d_latch IS
	PORT(enable, data	: IN BIT;   --ena输入使能，data输入数据
		 q		        : OUT BIT); --锁存器输出
END d_latch;
ARCHITECTURE rtl OF d_latch IS
BEGIN
	PROCESS(enable, data)
	BEGIN
		IF (enable = '1') THEN		 --enable有