statemachine2.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY statemachine2 IS
	PORT(clk 				: IN STD_LOGIC;						--全局时钟
		 keyvalue			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);	--按键值
		 keypressed			: IN STD_LOGIC;                     --有按键来标志
		 alarmon 			: OUT STD_LOGIC;                    --闹钟时间加载信号 
		 houralarmon			: OUT STD_LOGIC);               --计时器时间加载信号
END statemachine2;
ARCHITECTURE rtl OF statemachine2 IS
	--定义2个状态的状态机
	TYPE state IS (S_off,s_on);
	--闹钟开关状态机的现态和次态
	SIGNAL ps_alarmon    		: state:=s_off;
	SIGNAL ns_alarmon    		: state:=s_off;
	--整点报时状态机的现态和次态
	SIGNAL ps_houralarmon  	  	: state:=s_off;
	SIGNAL ns_houralarmon  	  	: state:=s_off;
BEGIN
	--状态更新
	PROCESS(clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			ps_alarmon <= ns_alarmon;
			ps_houralarmon <= ns_houralarmon;
		END IF;
	END PROCESS;
	--闹钟开关状态机的状态译码和输出译码
	PROCESS(ps_alarmon,keypressed,keyvalue)
	BEGIN
		IF(ps_alarmon=s_on)THEN
			IF(keypressed='1' AND keyvalue="1100")THEN
				ns_alarmon <= s_off;
			ELSE
				ns_alarmon <= ps_alarmon;
			END IF;
			alarmon <= '1';
		ELSE
			IF(keypressed='1' AND keyvalue="1100")THEN
				ns_alarmon <= s_on;
			ELSE
				ns_alarmon <= ps_alarmon;
			END IF;
			alarmon <= '0';
		END IF;	
	END PROCESS;
	----整点报时开关状态机的状态译码和输出译码
	PROCESS(ps_houralarmon,keypressed,keyvalue)
	BEGIN
		IF(ps_houralarmon=s_on)THEN
			IF(keypressed='1' AND keyvalue="1101")THEN
				ns_houralarmon <= s_off;
			ELSE
				ns_houralarmon <= ps_houralarmon;
			END IF;
			houralarmon <= '1';
		ELSE
			IF(keypressed='1' AND keyvalue="1101")THEN
				ns_houralarmon <= s_on;
			ELSE
				ns_houralarmon <= ps_houralarmon;
			END IF;
			houralarmon <= '0';
		END IF;	
	END PROCESS;
END rtl;