counter.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter IS
	PORT(clk 				: IN STD_LOGIC;							--全局时钟
		 load 				: IN STD_LOGIC;                         --同步加载信号
		 buffertime 		: IN STD_LOGIC_VECTOR(23 DOWNTO 0);     --同步加载数据
		 time				: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));   --当前时间输出
END counter;
ARCHITECTURE rtl OF counter IS
	SIGNAL clk1s			: STD_LOGIC;                            --频率为1HZ的信号
	SIGNAL time_sig         : STD_LOGIC_VECTOR(23 DOWNTO 0);        --当前时间的信号表示
	--1000000分频计数器说明
	COMPONENT divider_1m
		PORT(
			clk		: IN	STD_LOGIC;                              --全局时钟
			clk1s	: OUT	STD_LOGIC);                             --频率为1HZ的信号
	END COMPONENT; 
BEGIN
	--1000000分频计数器实例化
	divider1M: divider_1m 
		PORT MAP (clk => clk, 
		          clk1s => clk1s);
	--时间计数器
	PROCESS(clk1s,clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			--同步加载
			IF(load='1')THEN
				time_sig <= buffertime;
			ELSE 
				--计数使能
				IF(clk1s='1')THEN
					--计数
					IF(time_sig(3 DOWNTO 0)="1001")THEN
						time_sig(3 DOWNTO 0) <= "0000";
						IF(time_sig(7 DOWNTO 4)="0101")THEN
							time_sig(7 DOWNTO 4) <= "0000";
							IF(time_sig(11 DOWNTO 8)="1001")THEN
								time_sig(11 DOWNTO 8) <= "0000";
								IF(time_sig(15 DOWNTO 12)="0101")THEN
									time_sig(15 DOWNTO 12) <= "0000";
									IF(time_sig(23 DOWNTO 16)="001001")THEN
										time_sig(23 DOWNTO 16) <= "010000";
										ELSIF(time_sig(23 DOWNTO 16)="011001")THEN
										time_sig(23 DOWNTO 16) <= "100000";
									ELSIF(time_sig(23 DOWNTO 16)="100011")THEN
										time_sig(23 DOWNTO 16) <= "000000";
									ELSE
										time_sig(23 DOWNTO 16) <= time_sig(23 DOWNTO 16) + 1 ;
									END IF;
								ELSE
									time_sig(15 DOWNTO 12) <= time_sig(15 DOWNTO 12) + 1 ;
								END IF;
							ELSE
								time_sig(11 DOWNTO 8) <= time_sig(11 DOWNTO 8) + 1 ;
							END IF;
						ELSE
							time_sig(7 DOWNTO 4) <= time_sig(7 DOWNTO 4) + 1 ;
						END IF;
					ELSE
						time_sig(3 DOWNTO 0) <= time_sig(3 DOWNTO 0) + 1 ;
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;
	--时间输出
	time <= time_sig;
END rtl;