alarmreg.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alarmreg IS
	PORT(alarmload 			: IN STD_LOGIC;							--并行加载的控制信号
		 clk				: IN STD_LOGIC;							--全局时钟
		 buffertime			: IN STD_LOGIC_VECTOR(23 DOWNTO 0);		--并行加载数据输入					
		 alarmtime			: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));   --寄存器输出
END alarmreg;
ARCHITECTURE rtl OF alarmreg IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			IF(alarmload='1')THEN
				alarmtime <= buffertime; 
			END IF;
		END IF;
	END PROCESS;
END rtl;