subber8_arith.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_ARITH.ALL;							--算术运算包
ENTITY subber8_arith IS
PORT(
		cin		: IN	STD_LOGIC;						--进位输入
        a,b     : IN    UNSIGNED(7 DOWNTO 0);			--被减数和减数
		s   	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--差
        cout    : OUT   STD_LOGIC);						--借位输出
END subber8_arith;
ARCHITECTURE rtl OF subber8_arith IS
	  SIGNAL temp  : STD_LOGIC_VECTOR(8 DOWNTO 0);      --借位输出与差的序列合并
BEGIN
	temp<= ('0' & a) - ('0' & b)- cin;
	s<=temp(7 DOWNTO 0);
	cout<=temp(8);
END rtl;