adder8_lookahead.vhd

这是一些经典的vhdl example

Library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;

ENTITY adder8_lookahead IS
	GENERIC (BR : INTEGER := 16);  		-- 加法器位数参数
	PORT (	
		a, b		: IN	STD_LOGIC_VECTOR ((BR-1) DOWNTO 0);		--输入加数
		carry_in	: IN	STD_LOGIC;								--输入进位
		s			: OUT   STD_LOGIC_VECTOR ((BR-1) DOWNTO 0);		--和
		carry_out	: OUT	STD_LOGIC								--输出进位
	     );
END adder8_lookahead;

ARCHITECTURE verhalten OF adder8_lookahead IS
SIGNAL	carry	:STD_LOGIC_VECTOR (BR-1 DOWNTO 0);
BEGIN
   cla: PROCESS(a,b,carry_in) 
	   VARIABLE p	: STD_LOGIC_VECTOR ((BR-1) DOWNTO 0);	--进位传送函数
	   VARIABLE g   : STD_LOGIC_VECTOR ((BR-1) DOWNTO 0);	--进位生成函数
	   VARIABLE c   : STD_LOGIC_VECTOR ( BR    DOWNTO 0);	--各级进位输出
	   VARIABLE cin  : STD_LOGIC_VECTOR ( BR    DOWNTO 0);	--各级进位输出
	BEGIN
	   FOR i IN 0 TO (BR-1) LOOP							
	      g(i) := a(i) AND b(i);							--进位传送函数和生成函数表达式
	      p(i) := a(i) OR b(i);
	   END LOOP;

	   c(0) := carry_in ;									--最低位进位
	   --cin(0):=carry_in ;
	   FOR i IN 0 TO (BR-1) LOOP							--进位表达式
	      c(i+1) := g(i) OR (p(i) AND c(i));
	   END LOOP;

	   FOR i IN 0 TO (BR-1) LOOP
	       carry(i) <= c(i);								--把本进程进位变量c赋给carry信号
	   END LOOP;
	   carry_out <= c(BR);									--进位输出
	END PROCESS;
   sum:	PROCESS(a,b,carry)
	-- eigentliche Addition
	BEGIN
	   FOR i IN 0 TO (BR-1) LOOP							--加法和表达式
	      s(i) <= a(i) XOR b(i) XOR carry(i);
	   END LOOP;
	END PROCESS;
END verhalten;