adder8_arith.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_ARITH.ALL;							--算术运算包
ENTITY adder8_arith IS
PORT(
		cin		: IN	STD_LOGIC;						--进位输入
        a,b     : IN    UNSIGNED(7 DOWNTO 0);			--加数
		s   	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--和
        cout    : OUT   STD_LOGIC);						--进位输出
END adder8_arith;
ARCHITECTURE rtl OF adder8_arith IS
	  SIGNAL temp  : STD_LOGIC_VECTOR(8 DOWNTO 0);      --进位输出与加法和的序列合并
BEGIN
	temp<= ('0' & a) + ('0' & b)+cin;
	s<=temp(7 DOWNTO 0);
	cout<=temp(8);
END rtl;