subber8_useadder.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_ARITH.ALL;							--算术运算包
ENTITY subber8_useadder IS
PORT(
		cin		: IN	STD_LOGIC;						--进位输入
        a,b     : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);	--被减数和减数
		s   	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--差
        cout    : OUT   STD_LOGIC);						--借位输出
END subber8_useadder;
ARCHITECTURE rtl OF subber8_useadder IS					
COMPONENT adder8										--引用8位加法器
PORT(
 	  	cin		: IN	STD_LOGIC;						--进位输入
        a,b     : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);	--加数
		s   	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--和
        cout    : OUT   STD_LOGIC);						--进位输出
END COMPONENT;
SIGNAL notcin	:STD_LOGIC;								--输入进位的非
SIGNAL notb		:STD_LOGIC_VECTOR(7 DOWNTO 0);			--输入减数的非
SIGNAL adder_cout	:STD_LOGIC;							--加法的输出进位=减法器输出进位的非						  
BEGIN
	notb<=not b;
	notcin<=not cin;
	subber_useadder:adder8
		PORT MAP (notcin, a,notb,
		          s,adder_cout);
   cout<=not adder_cout;
END rtl;