ex11.hier_info

点阵显示的vhdl程序,是一个学员实验用的程序

|Block1
COL[0] <= W_ROM:inst6.COL[0]
COL[1] <= W_ROM:inst6.COL[1]
COL[2] <= W_ROM:inst6.COL[2]
COL[3] <= W_ROM:inst6.COL[3]
COL[4] <= W_ROM:inst6.COL[4]
COL[5] <= W_ROM:inst6.COL[5]
COL[6] <= W_ROM:inst6.COL[6]
COL[7] <= W_ROM:inst6.COL[7]
CLK => W_ROM:inst6.CLK
CLK => CNT:inst5.CLK
ROW[0] <= lpm_rom0:inst.q[0]
ROW[1] <= lpm_rom0:inst.q[1]
ROW[2] <= lpm_rom0:inst.q[2]
ROW[3] <= lpm_rom0:inst.q[3]
ROW[4] <= lpm_rom0:inst.q[4]
ROW[5] <= lpm_rom0:inst.q[5]
ROW[6] <= lpm_rom0:inst.q[6]
ROW[7] <= lpm_rom0:inst.q[7]


|Block1|W_ROM:inst6
ADDRESS_IN[0] => Add1.IN16
ADDRESS_IN[0] => ADDRESS_SHIFT~7.DATAB
ADDRESS_IN[0] => Add3.IN16
ADDRESS_IN[0] => ADDRESS_SHIFT~23.DATAB
ADDRESS_IN[0] => Add5.IN16
ADDRESS_IN[0] => ADDRESS_SHIFT~39.DATAB
ADDRESS_IN[0] => Add7.IN16
ADDRESS_IN[0] => ADDRESS_SHIFT~55.DATAB
ADDRESS_IN[1] => Add1.IN15
ADDRESS_IN[1] => Add2.IN14
ADDRESS_IN[1] => Add3.IN15
ADDRESS_IN[1] => ADDRESS_SHIFT~22.DATAB
ADDRESS_IN[1] => Add5.IN15
ADDRESS_IN[1] => Add6.IN14
ADDRESS_IN[1] => Add7.IN15
ADDRESS_IN[1] => ADDRESS_SHIFT~54.DATAB
ADDRESS_IN[2] => Add1.IN14
ADDRESS_IN[2] => Add2.IN13
ADDRESS_IN[2] => Add3.IN14
ADDRESS_IN[2] => Add4.IN12
ADDRESS_IN[2] => Add5.IN14
ADDRESS_IN[2] => Add6.IN13
ADDRESS_IN[2] => Add7.IN14
ADDRESS_IN[2] => ADDRESS_SHIFT~53.DATAB
ADDRESS_IN[3] => Add1.IN13
ADDRESS_IN[3] => Add2.IN12
ADDRESS_IN[3] => Add3.IN13
ADDRESS_IN[3] => Add4.IN11
ADDRESS_IN[3] => Add5.IN13
ADDRESS_IN[3] => Add6.IN12
ADDRESS_IN[3] => Add7.IN13
ADDRESS_IN[3] => ADDRESS_SHIFT~52.DATAB
ADDRESS_IN[4] => Add1.IN12
ADDRESS_IN[4] => Add2.IN11
ADDRESS_IN[4] => Add3.IN12
ADDRESS_IN[4] => Add4.IN10
ADDRESS_IN[4] => Add5.IN12
ADDRESS_IN[4] => Add6.IN11
ADDRESS_IN[4] => Add7.IN12
ADDRESS_IN[4] => ADDRESS_SHIFT~51.DATAB
ADDRESS_IN[5] => Add1.IN11
ADDRESS_IN[5] => Add2.IN10
ADDRESS_IN[5] => Add3.IN11
ADDRESS_IN[5] => Add4.IN9
ADDRESS_IN[5] => Add5.IN11
ADDRESS_IN[5] => Add6.IN10
ADDRESS_IN[5] => Add7.IN11
ADDRESS_IN[5] => ADDRESS_SHIFT~50.DATAB
ADDRESS_IN[6] => Add1.IN10
ADDRESS_IN[6] => Add2.IN9
ADDRESS_IN[6] => Add3.IN10
ADDRESS_IN[6] => Add4.IN8
ADDRESS_IN[6] => Add5.IN10
ADDRESS_IN[6] => Add6.IN9
ADDRESS_IN[6] => Add7.IN10
ADDRESS_IN[6] => ADDRESS_SHIFT~49.DATAB
ADDRESS_IN[7] => Add1.IN9
ADDRESS_IN[7] => Add2.IN8
ADDRESS_IN[7] => Add3.IN9
ADDRESS_IN[7] => Add4.IN7
ADDRESS_IN[7] => Add5.IN9
ADDRESS_IN[7] => Add6.IN8
ADDRESS_IN[7] => Add7.IN9
ADDRESS_IN[7] => ADDRESS_SHIFT~48.DATAB
CLK => CNT[0].CLK
CLK => CNT[1].CLK
CLK => CNT[2].CLK
COL[0] <= COL~26.DB_MAX_OUTPUT_PORT_TYPE
COL[1] <= COL~25.DB_MAX_OUTPUT_PORT_TYPE
COL[2] <= COL~24.DB_MAX_OUTPUT_PORT_TYPE
COL[3] <= COL~23.DB_MAX_OUTPUT_PORT_TYPE
COL[4] <= COL~22.DB_MAX_OUTPUT_PORT_TYPE
COL[5] <= COL~21.DB_MAX_OUTPUT_PORT_TYPE
COL[6] <= COL~20.DB_MAX_OUTPUT_PORT_TYPE
COL[7] <= Equal6.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[0] <= ADDRESS_SHIFT~55.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[1] <= ADDRESS_SHIFT~54.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[2] <= ADDRESS_SHIFT~53.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[3] <= ADDRESS_SHIFT~52.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[4] <= ADDRESS_SHIFT~51.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[5] <= ADDRESS_SHIFT~50.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[6] <= ADDRESS_SHIFT~49.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS_ROW[7] <= ADDRESS_SHIFT~48.DB_MAX_OUTPUT_PORT_TYPE


|Block1|CNT:inst5
CLK => CNT[0].CLK
CLK => CNT[1].CLK
CLK => CNT[2].CLK
CLK => CNT[3].CLK
CLK => CNT[4].CLK
CLK => CNT[5].CLK
CLK => CNT[6].CLK
CLK => CNT[7].CLK
CLK => CNT[8].CLK
CLK => CNT[9].CLK
CLK => CNT[10].CLK
CLK => CNT[11].CLK
CLK => CNT[12].CLK
CNT_OUT[0] <= CNT_OUT~4.DB_MAX_OUTPUT_PORT_TYPE
CNT_OUT[1] <= CNT_OUT~3.DB_MAX_OUTPUT_PORT_TYPE
CNT_OUT[2] <= <GND>
CNT_OUT[3] <= <GND>
CNT_OUT[4] <= <GND>
CNT_OUT[5] <= <GND>
CNT_OUT[6] <= <GND>
CNT_OUT[7] <= <GND>


|Block1|lpm_rom0:inst
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
address[7] => lpm_rom:lpm_rom_component.address[7]
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]
q[6] <= lpm_rom:lpm_rom_component.q[6]
q[7] <= lpm_rom:lpm_rom_component.q[7]


|Block1|lpm_rom0:inst|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => ~NO_FANOUT~
outclock => ~NO_FANOUT~
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE


|Block1|lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => ~NO_FANOUT~
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT