📄 ex11.tan.qmsg
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "Block1.bdf" "" { Schematic "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/Block1.bdf" { { 208 -336 -168 224 "CLK" "" } } } } { "d:/altera/qii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/qii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CNT:inst5\|CNT\[3\] register CNT:inst5\|CNT\[12\] 90.91 MHz 11.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 90.91 MHz between source register \"CNT:inst5\|CNT\[3\]\" and destination register \"CNT:inst5\|CNT\[12\]\" (period= 11.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.800 ns + Longest register register " "Info: + Longest register to register delay is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT:inst5\|CNT\[3\] 1 REG LC1_B15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B15; Fanout = 4; REG Node = 'CNT:inst5\|CNT\[3\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT:inst5|CNT[3] } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 2.900 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 2 COMB LC6_B14 2 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 2.900 ns; Loc. = LC6_B14; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { CNT:inst5|CNT[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.100 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 3 COMB LC7_B14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 3.100 ns; Loc. = LC7_B14; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.300 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 4 COMB LC8_B14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 3.300 ns; Loc. = LC8_B14; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 4.000 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 5 COMB LC1_B16 2 " "Info: 5: + IC(0.500 ns) + CELL(0.200 ns) = 4.000 ns; Loc. = LC1_B16; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.700 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.200 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 6 COMB LC2_B16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 4.200 ns; Loc. = LC2_B16; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.400 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 7 COMB LC3_B16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 4.400 ns; Loc. = LC3_B16; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.600 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 8 COMB LC4_B16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 4.600 ns; Loc. = LC4_B16; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.800 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 9 COMB LC5_B16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = LC5_B16; Fanout = 2; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 10 COMB LC6_B16 1 " "Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = LC6_B16; Fanout = 1; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 6.100 ns CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[12\] 11 COMB LC7_B16 1 " "Info: 11: + IC(0.000 ns) + CELL(1.100 ns) = 6.100 ns; Loc. = LC7_B16; Fanout = 1; COMB Node = 'CNT:inst5\|lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[12\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] CNT:inst5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12] } "NODE_NAME" } } { "addcore.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/addcore.tdf" 95 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.900 ns) 8.800 ns CNT:inst5\|CNT\[12\] 12 REG LC6_B13 7 " "Info: 12: + IC(1.800 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC6_B13; Fanout = 7; REG Node = 'CNT:inst5\|CNT\[12\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { CNT:inst5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12] CNT:inst5|CNT[12] } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 51.14 % ) " "Info: Total cell delay = 4.500 ns ( 51.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 48.86 % ) " "Info: Total interconnect delay = 4.300 ns ( 48.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { CNT:inst5|CNT[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] CNT:inst5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12] CNT:inst5|CNT[12] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "8.800 ns" { CNT:inst5|CNT[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] CNT:inst5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12] CNT:inst5|CNT[12] } { 0.000ns 2.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 0.900ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.100ns 0.900ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/Block1.bdf" { { 208 -336 -168 224 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns CNT:inst5\|CNT\[12\] 2 REG LC6_B13 7 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_B13; Fanout = 7; REG Node = 'CNT:inst5\|CNT\[12\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { CLK CNT:inst5|CNT[12] } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[12] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[12] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/Block1.bdf" { { 208 -336 -168 224 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns CNT:inst5\|CNT\[3\] 2 REG LC1_B15 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B15; Fanout = 4; REG Node = 'CNT:inst5\|CNT\[3\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { CLK CNT:inst5|CNT[3] } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[3] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[12] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[12] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[3] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { CNT:inst5|CNT[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] CNT:inst5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12] CNT:inst5|CNT[12] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "8.800 ns" { CNT:inst5|CNT[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] CNT:inst5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12] CNT:inst5|CNT[12] } { 0.000ns 2.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 0.900ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.100ns 0.900ns } "" } } { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[12] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[12] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[3] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK ROW\[0\] CNT:inst5\|CNT\[10\] 54.500 ns register " "Info: tco from clock \"CLK\" to destination pin \"ROW\[0\]\" through register \"CNT:inst5\|CNT\[10\]\" is 54.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/Block1.bdf" { { 208 -336 -168 224 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns CNT:inst5\|CNT\[10\] 2 REG LC5_B13 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B13; Fanout = 4; REG Node = 'CNT:inst5\|CNT\[10\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { CLK CNT:inst5|CNT[10] } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[10] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[10] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "49.700 ns + Longest register pin " "Info: + Longest register to pin delay is 49.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT:inst5\|CNT\[10\] 1 REG LC5_B13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B13; Fanout = 4; REG Node = 'CNT:inst5\|CNT\[10\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT:inst5|CNT[10] } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 3.700 ns CNT:inst5\|LessThan4~93 2 COMB LC8_B16 2 " "Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 3.700 ns; Loc. = LC8_B16; Fanout = 2; COMB Node = 'CNT:inst5\|LessThan4~93'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { CNT:inst5|CNT[10] CNT:inst5|LessThan4~93 } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.400 ns) 7.000 ns CNT:inst5\|LessThan4~94 3 COMB LC6_B23 3 " "Info: 3: + IC(1.900 ns) + CELL(1.400 ns) = 7.000 ns; Loc. = LC6_B23; Fanout = 3; COMB Node = 'CNT:inst5\|LessThan4~94'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { CNT:inst5|LessThan4~93 CNT:inst5|LessThan4~94 } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 9.500 ns CNT:inst5\|CNT_OUT~462 4 COMB LC7_B23 1 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 9.500 ns; Loc. = LC7_B23; Fanout = 1; COMB Node = 'CNT:inst5\|CNT_OUT~462'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CNT:inst5|LessThan4~94 CNT:inst5|CNT_OUT~462 } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 12.000 ns CNT:inst5\|CNT_OUT~463 5 COMB LC1_B23 3 " "Info: 5: + IC(0.600 ns) + CELL(1.900 ns) = 12.000 ns; Loc. = LC1_B23; Fanout = 3; COMB Node = 'CNT:inst5\|CNT_OUT~463'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CNT:inst5|CNT_OUT~462 CNT:inst5|CNT_OUT~463 } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 14.500 ns CNT:inst5\|CNT_OUT~464 6 COMB LC8_B23 1 " "Info: 6: + IC(0.600 ns) + CELL(1.900 ns) = 14.500 ns; Loc. = LC8_B23; Fanout = 1; COMB Node = 'CNT:inst5\|CNT_OUT~464'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CNT:inst5|CNT_OUT~463 CNT:inst5|CNT_OUT~464 } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 16.500 ns CNT:inst5\|CNT_OUT\[0\]~465 7 COMB LC2_B23 4 " "Info: 7: + IC(0.600 ns) + CELL(1.400 ns) = 16.500 ns; Loc. = LC2_B23; Fanout = 4; COMB Node = 'CNT:inst5\|CNT_OUT\[0\]~465'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { CNT:inst5|CNT_OUT~464 CNT:inst5|CNT_OUT[0]~465 } "NODE_NAME" } } { "CNT.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/CNT.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.900 ns) 20.900 ns W_ROM:inst6\|Add7~27 8 COMB LC4_A21 2 " "Info: 8: + IC(2.500 ns) + CELL(1.900 ns) = 20.900 ns; Loc. = LC4_A21; Fanout = 2; COMB Node = 'W_ROM:inst6\|Add7~27'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { CNT:inst5|CNT_OUT[0]~465 W_ROM:inst6|Add7~27 } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/qii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 24.600 ns W_ROM:inst6\|ADDRESS_ROW\[2\]~995 9 COMB LC8_A13 1 " "Info: 9: + IC(1.800 ns) + CELL(1.900 ns) = 24.600 ns; Loc. = LC8_A13; Fanout = 1; COMB Node = 'W_ROM:inst6\|ADDRESS_ROW\[2\]~995'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { W_ROM:inst6|Add7~27 W_ROM:inst6|ADDRESS_ROW[2]~995 } "NODE_NAME" } } { "W_ROM.vhd" "" { Text "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/W_ROM.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 26.600 ns lpm_rom0:inst\|lpm_rom:lpm_rom_component\|altrom:srom\|segment\[0\]\[7\]~0 10 COMB LC1_A13 8 " "Info: 10: + IC(0.600 ns) + CELL(1.400 ns) = 26.600 ns; Loc. = LC1_A13; Fanout = 8; COMB Node = 'lpm_rom0:inst\|lpm_rom:lpm_rom_component\|altrom:srom\|segment\[0\]\[7\]~0'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { W_ROM:inst6|ADDRESS_ROW[2]~995 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]~0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/altrom.tdf" 129 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(10.200 ns) 39.100 ns lpm_rom0:inst\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~mem_cell_ra0 11 MEM EC4_A 1 " "Info: 11: + IC(2.300 ns) + CELL(10.200 ns) = 39.100 ns; Loc. = EC4_A; Fanout = 1; MEM Node = 'lpm_rom0:inst\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~mem_cell_ra0'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "12.500 ns" { lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]~0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 41.100 ns lpm_rom0:inst\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] 12 MEM EC4_A 1 " "Info: 12: + IC(0.000 ns) + CELL(2.000 ns) = 41.100 ns; Loc. = EC4_A; Fanout = 1; MEM Node = 'lpm_rom0:inst\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/qii7.0/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.400 ns) 44.900 ns ROW\[0\]~7 13 COMB LC4_A12 1 " "Info: 13: + IC(2.400 ns) + CELL(1.400 ns) = 44.900 ns; Loc. = LC4_A12; Fanout = 1; COMB Node = 'ROW\[0\]~7'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0] ROW[0]~7 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/Block1.bdf" { { 328 720 896 344 "ROW\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(3.900 ns) 49.700 ns ROW\[0\] 14 PIN PIN_39 0 " "Info: 14: + IC(0.900 ns) + CELL(3.900 ns) = 49.700 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'ROW\[0\]'" { } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { ROW[0]~7 ROW[0] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/altera/QII7.0/quartus/excise/EX11模块化的点阵/Block1.bdf" { { 328 720 896 344 "ROW\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "33.100 ns ( 66.60 % ) " "Info: Total cell delay = 33.100 ns ( 66.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.600 ns ( 33.40 % ) " "Info: Total interconnect delay = 16.600 ns ( 33.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "49.700 ns" { CNT:inst5|CNT[10] CNT:inst5|LessThan4~93 CNT:inst5|LessThan4~94 CNT:inst5|CNT_OUT~462 CNT:inst5|CNT_OUT~463 CNT:inst5|CNT_OUT~464 CNT:inst5|CNT_OUT[0]~465 W_ROM:inst6|Add7~27 W_ROM:inst6|ADDRESS_ROW[2]~995 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]~0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0] ROW[0]~7 ROW[0] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "49.700 ns" { CNT:inst5|CNT[10] CNT:inst5|LessThan4~93 CNT:inst5|LessThan4~94 CNT:inst5|CNT_OUT~462 CNT:inst5|CNT_OUT~463 CNT:inst5|CNT_OUT~464 CNT:inst5|CNT_OUT[0]~465 W_ROM:inst6|Add7~27 W_ROM:inst6|ADDRESS_ROW[2]~995 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]~0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0] ROW[0]~7 ROW[0] } { 0.000ns 1.800ns 1.900ns 0.600ns 0.600ns 0.600ns 0.600ns 2.500ns 1.800ns 0.600ns 2.300ns 0.000ns 2.400ns 0.900ns } { 0.000ns 1.900ns 1.400ns 1.900ns 1.900ns 1.900ns 1.400ns 1.900ns 1.900ns 1.400ns 10.200ns 2.000ns 1.400ns 3.900ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { CLK CNT:inst5|CNT[10] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { CLK CLK~out CNT:inst5|CNT[10] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/qii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "49.700 ns" { CNT:inst5|CNT[10] CNT:inst5|LessThan4~93 CNT:inst5|LessThan4~94 CNT:inst5|CNT_OUT~462 CNT:inst5|CNT_OUT~463 CNT:inst5|CNT_OUT~464 CNT:inst5|CNT_OUT[0]~465 W_ROM:inst6|Add7~27 W_ROM:inst6|ADDRESS_ROW[2]~995 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]~0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0] ROW[0]~7 ROW[0] } "NODE_NAME" } } { "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/qii7.0/quartus/bin/Technology_Viewer.qrui" "49.700 ns" { CNT:inst5|CNT[10] CNT:inst5|LessThan4~93 CNT:inst5|LessThan4~94 CNT:inst5|CNT_OUT~462 CNT:inst5|CNT_OUT~463 CNT:inst5|CNT_OUT~464 CNT:inst5|CNT_OUT[0]~465 W_ROM:inst6|Add7~27 W_ROM:inst6|ADDRESS_ROW[2]~995 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]~0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0] ROW[0]~7 ROW[0] } { 0.000ns 1.800ns 1.900ns 0.600ns 0.600ns 0.600ns 0.600ns 2.500ns 1.800ns 0.600ns 2.300ns 0.000ns 2.400ns 0.900ns } { 0.000ns 1.900ns 1.400ns 1.900ns 1.900ns 1.900ns 1.400ns 1.900ns 1.900ns 1.400ns 10.200ns 2.000ns 1.400ns 3.900ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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