cnt.vhd

点阵显示的vhdl程序,是一个学员实验用的程序

------JISHUQI
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT IS 
PORT (
   CLK : IN STD_LOGIC;   -----控制了扫描的频率   
   CNT_OUT  :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  ----选择发光的阵列
);
END CNT;

ARCHITECTURE BEHV OF CNT IS  
SIGNAL CNT : INTEGER RANGE 0 TO 7999;
BEGIN 
  PROCESS(CLK)
    BEGIN
      IF RISING_EDGE(CLK) THEN 
        IF CNT= 7999 THEN 
           CNT<=0 ;
        ELSE 
          CNT<=CNT+1;
        END IF;
      END IF;
  END PROCESS;
  CNT_OUT<="00000000" WHEN CNT<2000 ELSE 
           "00000001" WHEN CNT>2000 AND CNT<4000 ELSE 
           "00000010" WHEN CNT>4000 AND CNT<6000 ELSE 
           "00000011" ;
END BEHV;