w_rom.vhd

点阵显示的vhdl程序,是一个学员实验用的程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY W_ROM IS 
 PORT  (
     ADDRESS_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     CLK   :IN STD_LOGIC;
     COL   :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     ADDRESS_ROW :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
 END W_ROM;

ARCHITECTURE SYN OF W_ROM IS 
  SIGNAL ADDRESS_SHIFT  :STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL CNT        :STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN  
  PROCESS(CLK)
   BEGIN 
     IF RISING_EDGE(CLK)  THEN 
       CNT<=CNT+1 ;
     END IF;
END PROCESS;

COL<= "10000000" WHEN CNT="000"   ELSE 
       "01000000" WHEN CNT="001"   ELSE
       "00100000" WHEN CNT="010"    ELSE
       "00010000" WHEN CNT="011"  ELSE
       "00001000" WHEN CNT="100"  ELSE
       "00000100" WHEN CNT="101"   ELSE
       "00000010" WHEN CNT="110"   ELSE
       "00000001" ;
ADDRESS_SHIFT<= ADDRESS_IN WHEN CNT="000" ELSE
       ADDRESS_IN+"00000001"  WHEN CNT="001" ELSE
       ADDRESS_IN+"00000010" WHEN CNT="010" ELSE
       ADDRESS_IN+"00000011" WHEN CNT="011" ELSE
       ADDRESS_IN+"00000100" WHEN CNT="100" ELSE
       ADDRESS_IN+"00000101" WHEN CNT="101" ELSE
       ADDRESS_IN+"00000110" WHEN CNT="110" ELSE
       ADDRESS_IN+"00000111" ;
ADDRESS_ROW<=ADDRESS_SHIFT;
END SYN;