ex11.tan.rpt

点阵显示的vhdl程序,是一个学员实验用的程序

; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[2] ; ROW[0] ; CLK        ;
; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[1] ; ROW[1] ; CLK        ;
; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[2] ; ROW[2] ; CLK        ;
; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[2] ; ROW[3] ; CLK        ;
; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[2] ; ROW[4] ; CLK        ;
; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[2] ; ROW[5] ; CLK        ;
; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[2] ; ROW[6] ; CLK        ;
; N/A   ; None         ; 37.000 ns  ; W_ROM:inst6|CNT[2] ; ROW[7] ; CLK        ;
; N/A   ; None         ; 36.900 ns  ; W_ROM:inst6|CNT[2] ; ROW[1] ; CLK        ;
; N/A   ; None         ; 14.400 ns  ; W_ROM:inst6|CNT[2] ; COL[1] ; CLK        ;
; N/A   ; None         ; 13.900 ns  ; W_ROM:inst6|CNT[0] ; COL[0] ; CLK        ;
; N/A   ; None         ; 13.900 ns  ; W_ROM:inst6|CNT[1] ; COL[1] ; CLK        ;
; N/A   ; None         ; 13.700 ns  ; W_ROM:inst6|CNT[0] ; COL[3] ; CLK        ;
; N/A   ; None         ; 13.700 ns  ; W_ROM:inst6|CNT[0] ; COL[4] ; CLK        ;
; N/A   ; None         ; 13.700 ns  ; W_ROM:inst6|CNT[0] ; COL[5] ; CLK        ;
; N/A   ; None         ; 13.700 ns  ; W_ROM:inst6|CNT[1] ; COL[6] ; CLK        ;
; N/A   ; None         ; 13.700 ns  ; W_ROM:inst6|CNT[2] ; COL[6] ; CLK        ;
; N/A   ; None         ; 13.200 ns  ; W_ROM:inst6|CNT[0] ; COL[2] ; CLK        ;
; N/A   ; None         ; 13.200 ns  ; W_ROM:inst6|CNT[0] ; COL[7] ; CLK        ;
; N/A   ; None         ; 13.100 ns  ; W_ROM:inst6|CNT[1] ; COL[0] ; CLK        ;
; N/A   ; None         ; 13.100 ns  ; W_ROM:inst6|CNT[2] ; COL[0] ; CLK        ;
; N/A   ; None         ; 13.100 ns  ; W_ROM:inst6|CNT[0] ; COL[1] ; CLK        ;
; N/A   ; None         ; 12.400 ns  ; W_ROM:inst6|CNT[1] ; COL[2] ; CLK        ;
; N/A   ; None         ; 12.400 ns  ; W_ROM:inst6|CNT[2] ; COL[2] ; CLK        ;
; N/A   ; None         ; 12.400 ns  ; W_ROM:inst6|CNT[1] ; COL[3] ; CLK        ;
; N/A   ; None         ; 12.400 ns  ; W_ROM:inst6|CNT[2] ; COL[4] ; CLK        ;
; N/A   ; None         ; 12.400 ns  ; W_ROM:inst6|CNT[2] ; COL[5] ; CLK        ;
; N/A   ; None         ; 11.900 ns  ; W_ROM:inst6|CNT[2] ; COL[3] ; CLK        ;
; N/A   ; None         ; 11.900 ns  ; W_ROM:inst6|CNT[1] ; COL[4] ; CLK        ;
; N/A   ; None         ; 11.900 ns  ; W_ROM:inst6|CNT[1] ; COL[5] ; CLK        ;
; N/A   ; None         ; 11.900 ns  ; W_ROM:inst6|CNT[0] ; COL[6] ; CLK        ;
; N/A   ; None         ; 11.900 ns  ; W_ROM:inst6|CNT[2] ; COL[7] ; CLK        ;
; N/A   ; None         ; 11.400 ns  ; W_ROM:inst6|CNT[1] ; COL[7] ; CLK        ;
+-------+--------------+------------+--------------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Jul 26 14:47:33 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off EX11 -c EX11
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 90.91 MHz between source register "CNT:inst5|CNT[3]" and destination register "CNT:inst5|CNT[12]" (period= 11.0 ns)
    Info: + Longest register to register delay is 8.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B15; Fanout = 4; REG Node = 'CNT:inst5|CNT[3]'
        Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 2.900 ns; Loc. = LC6_B14; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 3.100 ns; Loc. = LC7_B14; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 3.300 ns; Loc. = LC8_B14; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 5: + IC(0.500 ns) + CELL(0.200 ns) = 4.000 ns; Loc. = LC1_B16; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 4.200 ns; Loc. = LC2_B16; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7]'
        Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 4.400 ns; Loc. = LC3_B16; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8]'
        Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 4.600 ns; Loc. = LC4_B16; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9]'
        Info: 9: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = LC5_B16; Fanout = 2; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10]'
        Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = LC6_B16; Fanout = 1; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11]'
        Info: 11: + IC(0.000 ns) + CELL(1.100 ns) = 6.100 ns; Loc. = LC7_B16; Fanout = 1; COMB Node = 'CNT:inst5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12]'
        Info: 12: + IC(1.800 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC6_B13; Fanout = 7; REG Node = 'CNT:inst5|CNT[12]'
        Info: Total cell delay = 4.500 ns ( 51.14 % )
        Info: Total interconnect delay = 4.300 ns ( 48.86 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_B13; Fanout = 7; REG Node = 'CNT:inst5|CNT[12]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B15; Fanout = 4; REG Node = 'CNT:inst5|CNT[3]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tco from clock "CLK" to destination pin "ROW[0]" through register "CNT:inst5|CNT[10]" is 54.500 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B13; Fanout = 4; REG Node = 'CNT:inst5|CNT[10]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 49.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B13; Fanout = 4; REG Node = 'CNT:inst5|CNT[10]'
        Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 3.700 ns; Loc. = LC8_B16; Fanout = 2; COMB Node = 'CNT:inst5|LessThan4~93'
        Info: 3: + IC(1.900 ns) + CELL(1.400 ns) = 7.000 ns; Loc. = LC6_B23; Fanout = 3; COMB Node = 'CNT:inst5|LessThan4~94'
        Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 9.500 ns; Loc. = LC7_B23; Fanout = 1; COMB Node = 'CNT:inst5|CNT_OUT~462'
        Info: 5: + IC(0.600 ns) + CELL(1.900 ns) = 12.000 ns; Loc. = LC1_B23; Fanout = 3; COMB Node = 'CNT:inst5|CNT_OUT~463'
        Info: 6: + IC(0.600 ns) + CELL(1.900 ns) = 14.500 ns; Loc. = LC8_B23; Fanout = 1; COMB Node = 'CNT:inst5|CNT_OUT~464'
        Info: 7: + IC(0.600 ns) + CELL(1.400 ns) = 16.500 ns; Loc. = LC2_B23; Fanout = 4; COMB Node = 'CNT:inst5|CNT_OUT[0]~465'
        Info: 8: + IC(2.500 ns) + CELL(1.900 ns) = 20.900 ns; Loc. = LC4_A21; Fanout = 2; COMB Node = 'W_ROM:inst6|Add7~27'
        Info: 9: + IC(1.800 ns) + CELL(1.900 ns) = 24.600 ns; Loc. = LC8_A13; Fanout = 1; COMB Node = 'W_ROM:inst6|ADDRESS_ROW[2]~995'
        Info: 10: + IC(0.600 ns) + CELL(1.400 ns) = 26.600 ns; Loc. = LC1_A13; Fanout = 8; COMB Node = 'lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]~0'
        Info: 11: + IC(2.300 ns) + CELL(10.200 ns) = 39.100 ns; Loc. = EC4_A; Fanout = 1; MEM Node = 'lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0'
        Info: 12: + IC(0.000 ns) + CELL(2.000 ns) = 41.100 ns; Loc. = EC4_A; Fanout = 1; MEM Node = 'lpm_rom0:inst|lpm_rom:lpm_rom_component|altrom:srom|q[0]'
        Info: 13: + IC(2.400 ns) + CELL(1.400 ns) = 44.900 ns; Loc. = LC4_A12; Fanout = 1; COMB Node = 'ROW[0]~7'
        Info: 14: + IC(0.900 ns) + CELL(3.900 ns) = 49.700 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'ROW[0]'
        Info: Total cell delay = 33.100 ns ( 66.60 % )
        Info: Total interconnect delay = 16.600 ns ( 33.40 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Thu Jul 26 14:47:34 2007
    Info: Elapsed time: 00:00:01