__projnav.log

实现乒乓缓存

Module <pingpang> compiled
Analysis of file <"pingpang.prj"> failed.
--> 

Total memory usage is 77136 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "clk_contrl.v"
Module <clk_contrl> compiled
Compiling verilog file "front.v"
Module <front> compiled
Compiling verilog file "a_task.v"
Module <a_task> compiled
Compiling verilog file "b_task.v"
Module <b_task> compiled
Compiling verilog file "back.v"
Module <back> compiled
Compiling verilog file "pingpang.v"
Module <pingpang> compiled
No errors in compilation
Analysis of file <"pingpang.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:261 - "pingpang.v" line 37 Connection to output port 'out_a' does not match port size
WARNING:HDLCompilers:261 - "pingpang.v" line 38 Connection to output port 'out_b' does not match port size
WARNING:HDLCompilers:259 - "pingpang.v" line 39 Connection to input port 'indata_a' does not match port size
WARNING:HDLCompilers:259 - "pingpang.v" line 39 Connection to input port 'indata_b' does not match port size
Analyzing top module <pingpang>.
Module <pingpang> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <pingpang>.
Analyzing module <clk_contrl>.
Module <clk_contrl> is correct for synthesis.
 
Analyzing module <front>.
Module <front> is correct for synthesis.
 
Analyzing module <a_task>.
Module <a_task> is correct for synthesis.
 
Analyzing module <b_task>.
Module <b_task> is correct for synthesis.
 
Analyzing module <back>.
Module <back> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <back>.
    Related source file is "back.v".
    Found 1-bit register for signal <rdy>.
    Found 16-bit register for signal <out>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0001>.
    Summary:
	inferred  17 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <back> synthesized.


Synthesizing Unit <b_task>.
    Related source file is "b_task.v".
    Found 16-bit register for signal <out_b>.
    Found 1-bit register for signal <rdy_b>.
    Summary:
	inferred  17 D-type flip-flop(s).
Unit <b_task> synthesized.


Synthesizing Unit <a_task>.
    Related source file is "a_task.v".
    Found 16-bit register for signal <out_a>.
    Found 1-bit register for signal <rdy_a>.
    Summary:
	inferred  17 D-type flip-flop(s).
Unit <a_task> synthesized.


Synthesizing Unit <front>.
    Related source file is "front.v".
WARNING:Xst:1305 - Output <b> is never assigned. Tied to value 0000000000000000.
    Found 16-bit register for signal <a>.
    Found 1-bit register for signal <rdy_a>.
    Found 1-bit register for signal <rdy_b>.
    Found 1-bit register for signal <state>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <front> synthesized.


Synthesizing Unit <clk_contrl>.
    Related source file is "clk_contrl.v".
    Found 1-bit register for signal <clk_2_5m>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <clk_contrl> synthesized.


Synthesizing Unit <pingpang>.
    Related source file is "pingpang.v".
Unit <pingpang> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 11
 1-bit register                    : 7
 16-bit register                   : 4
# Multiplexers                     : 1
 1-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <a_15> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_1> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_2> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_3> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_4> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_5> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_6> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_7> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_8> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_9> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_10> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_11> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_12> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_13> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_14> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <out_a_15> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_14> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_1> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_2> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_3> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_4> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_5> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_6> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_7> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_8> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_9> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_10> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_11> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_12> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_a_13> is unconnected in block <a_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_15> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_14> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_1> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_2> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_3> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_4> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_5> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_6> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_7> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_8> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_9> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_10> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_11> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_12> is unconnected in block <b_task_1>.
WARNING:Xst:1291 - FF/Latch <out_b_13> is unconnected in block <b_task_1>.
Register <out_15> equivalent to <out_13> has been removed
Register <out_14> equivalent to <out_13> has been removed
Register <out_13> equivalent to <out_12> has been removed
Register <out_12> equivalent to <out_11> has been removed
Register <out_11> equivalent to <out_10> has been removed
Register <out_10> equivalent to <out_9> has been removed
Register <out_9> equivalent to <out_8> has been removed
Register <out_8> equivalent to <out_7> has been removed
Register <out_2> equivalent to <out_1> has been removed
Register <out_7> equivalent to <out_1> has been removed
Register <out_6> equivalent to <out_1> has been removed
Register <out_5> equivalent to <out_1> has been removed
Register <out_4> equivalent to <out_1> has been removed
Register <out_3> equivalent to <out_1> has been removed
WARNING:Xst:1710 - FF/Latch  <out_1> (without init value) has a constant value of 0 in block <back>.

Optimizing unit <pingpang> ...

Optimizing unit <back> ...

Optimizing unit <front> ...

Optimizing unit <a_task> ...

Optimizing unit <b_task> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/LijunYang_software/xilinx.

Mapping all equations...
WARNING:Xst:1426 - The value init of the FF/Latch b_task_1/out_b_0 hinder the constant cleaning in the block pingpang.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1291 - FF/Latch <front_1/a_13> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_13> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_13> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_15> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_14> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_1> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_2> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_3> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_4> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_5> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_6> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_7> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_8> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_9> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_10> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_11> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_12> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_15> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_14> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_1> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_2> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_3> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_4> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_5> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_6> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_7> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_8> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_9> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_10> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_11> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <a_task_1/out_a_12> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_15> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_14> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_1> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_2> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_3> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_4> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_5> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_6> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_7> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_8> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_9> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_10> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_11> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <b_task_1/out_b_12> is unconnected in block <pingpang>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pingpang, actual ratio is 0.
FlipFlop back_1/rdy has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                       8  out of   3584     0%  
 Number of Slice Flip Flops:            12  out of   7168     0%  
 Number of 4 input LUTs:                12  out of   7168     0%  
 Number of bonded IOBs:                 36  out of    141    25%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_contrl_1/clk_2_5m:Q            | NONE                   | 4     |
clk_5m                             | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.790ns (Maximum Frequency: 263.852MHz)
   Minimum input arrival time before clock: 4.088ns
   Maximum output required time after clock: 7.165ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "clk_contrl.v"
Module <clk_contrl> compiled
Compiling verilog file "front.v"
Module <front> compiled
Compiling verilog file "a_task.v"
Module <a_task> compiled
Compiling verilog file "b_task.v"
Module <b_task> compiled
Compiling verilog file "back.v"
Module <back> compiled
Compiling verilog file "pingpang.v"
Module <pingpang> compiled
No errors in compilation
Analysis of file <"pingpang.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:261 - "pingpang.v" line 36 Connection to output port 'out_a' does not match port size
WARNING:HDLCompilers:261 - "pingpang.v" line 37 Connection to output port 'out_b' does not match port size
WARNING:HDLCompilers:259 - "pingpang.v" line 38 Connection to input port 'indata_a' does not match port size
WARNING:HDLCompilers:259 - "pingpang.v" line 38 Connection to input port 'indata_b' does not match port size
Analyzing top module <pingpang>.
Module <pingpang> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <pingpang>.
Analyzing module <clk_contrl>.
Module <clk_cont