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Compiling verilog file "b_task.v"Module <b_task> compiledNo errors in compilationAnalysis of file <"b_task.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <b_task>.Module <b_task> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <b_task>. Related source file is "b_task.v". Found 16-bit register for signal <out_b>. Found 1-bit register for signal <rdy_b>. Summary: inferred 17 D-type flip-flop(s).Unit <b_task> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 2 1-bit register : 1 16-bit register : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <b_task> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/LijunYang_software/xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block b_task, actual ratio is 0.FlipFlop rdy_b has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4 Number of Slices: 10 out of 3584 0% Number of Slice Flip Flops: 18 out of 7168 0% Number of 4 input LUTs: 2 out of 7168 0% Number of bonded IOBs: 36 out of 141 25% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_2_5m | BUFGP | 18 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 3.746ns (Maximum Frequency: 266.951MHz) Minimum input arrival time before clock: 4.467ns Maximum output required time after clock: 7.165ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "back.v"ERROR:HDLCompilers:28 - "back.v" line 30 'rst' has not been declaredERROR:HDLCompilers:28 - "back.v" line 32 'rst' has not been declaredModule <back> compiledAnalysis of file <"back.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "back.v"Module <back> compiledERROR:HDLCompilers:247 - "back.v" line 35 Reference to scalar wire 'rdy' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "back.v" line 35 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "back.v" line 40 Reference to scalar wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "back.v" line 40 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "back.v" line 41 Reference to scalar wire 'rdy' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "back.v" line 41 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "back.v" line 45 Reference to scalar wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "back.v" line 45 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "back.v" line 46 Reference to scalar wire 'rdy' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "back.v" line 46 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "back.v" line 48 Reference to scalar wire 'rdy' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "back.v" line 48 Illegal left hand side of nonblocking assignmentAnalysis of file <"back.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors : 12 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "back.v"Module <back> compiledNo errors in compilationAnalysis of file <"back.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <back>.Module <back> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <back>. Related source file is "back.v". Found 1-bit register for signal <rdy>. Found 16-bit register for signal <out>. Found 1-bit 4-to-1 multiplexer for signal <$n0001>. Summary: inferred 17 D-type flip-flop(s). inferred 1 Multiplexer(s).Unit <back> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 2 1-bit register : 1 16-bit register : 1# Multiplexers : 1 1-bit 4-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <back> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/LijunYang_software/xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block back, actual ratio is 0.FlipFlop rdy has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4 Number of Slices: 11 out of 3584 0% Number of Slice Flip Flops: 18 out of 7168 0% Number of 4 input LUTs: 19 out of 7168 0% Number of bonded IOBs: 53 out of 141 37% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_5m | BUFGP | 18 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 3.619ns (Maximum Frequency: 276.319MHz) Minimum input arrival time before clock: 5.000ns Maximum output required time after clock: 7.165ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"Module <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"ERROR:HDLCompilers:27 - "pingpang.v" line 32 Illegal redeclaration of 'clk_2_5m'Module <pingpang> compiledAnalysis of file <"pingpang.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"Module <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"ERROR:HDLCompilers:27 - "pingpang.v" line 32 Illegal redeclaration of 'clk_2_5m'⌨️ 快捷键说明
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