__projnav.log

实现乒乓缓存

WARNING:HDLCompilers:259 - "pingpang.v" line 32 Connection to input port 'indata_b' does not match port size
WARNING:HDLCompilers:261 - "pingpang.v" line 32 Connection to output port 'out_b' does not match port size
WARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'indata_a' does not match port size
WARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'indata_b' does not match port size
WARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'out' does not match port size
Analyzing top module <pingpang>.
Module <pingpang> is correct for synthesis.
 
Analyzing module <clk_contrl>.
Module <clk_contrl> is correct for synthesis.
 
Analyzing module <front>.
Module <front> is correct for synthesis.
 
Analyzing module <a_task>.
Module <a_task> is correct for synthesis.
 
Analyzing module <b_task>.
Generating a Black Box for module <b_task>.
 
Analyzing module <back>.
Generating a Black Box for module <back>.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <a_task>.
    Related source file is "a_task.v".
    Found 16-bit register for signal <out_a>.
    Found 1-bit register for signal <rdy_a>.
    Summary:
	inferred  17 D-type flip-flop(s).
Unit <a_task> synthesized.


Synthesizing Unit <front>.
    Related source file is "front.v".
WARNING:Xst:1305 - Output <b> is never assigned. Tied to value 0000000000000000.
    Found 16-bit register for signal <a>.
    Found 1-bit register for signal <rdy_a>.
    Found 1-bit register for signal <rdy_b>.
    Found 1-bit register for signal <state>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <front> synthesized.


Synthesizing Unit <clk_contrl>.
    Related source file is "clk_contrl.v".
    Found 1-bit register for signal <clk_2_5m>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <clk_contrl> synthesized.


Synthesizing Unit <pingpang>.
    Related source file is "pingpang.v".
WARNING:Xst:1305 - Output <rdy> is never assigned. Tied to value 0.
WARNING:Xst:1306 - Output <out<15:1>> is never assigned.
WARNING:Xst:1305 - Output <out<0>> is never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <nd_a> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <nd_b> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <a> is assigned but never used.
WARNING:Xst:646 - Signal <b> is assigned but never used.
WARNING:Xst:653 - Signal <out_a> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <out_b> is assigned but never used.
WARNING:Xst:653 - Signal <indata_a> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <indata_b> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <rdy_a> is assigned but never used.
Unit <pingpang> synthesized.

WARNING:Xst:524 - All outputs of the instance <a_task_1> of the block <a_task> are unconnected in block <pingpang>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
 1-bit register                    : 4
 16-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <a_15> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <rdy_a> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_0> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_1> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_2> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_3> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_4> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_5> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_6> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_7> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_8> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_9> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_10> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_11> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_12> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_13> is unconnected in block <front_1>.
WARNING:Xst:1291 - FF/Latch <a_14> is unconnected in block <front_1>.

Optimizing unit <pingpang> ...

Optimizing unit <a_task> ...

Optimizing unit <front> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/LijunYang_software/xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <front_1/a_13> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_15> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_14> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/rdy_a> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_0> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_1> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_2> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_3> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_4> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_5> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_6> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_7> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_8> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_9> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_10> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_11> is unconnected in block <pingpang>.
WARNING:Xst:1291 - FF/Latch <front_1/a_12> is unconnected in block <pingpang>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pingpang, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                       2  out of   3584     0%  
 Number of Slice Flip Flops:             3  out of   7168     0%  
 Number of 4 input LUTs:                 2  out of   7168     0%  
 Number of bonded IOBs:                 36  out of    141    25%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_5m                             | BUFGP                  | 3     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.076ns (Maximum Frequency: 325.098MHz)
   Minimum input arrival time before clock: 2.791ns
   Maximum output required time after clock: 1.521ns
   Maximum combinational path delay: 1.308ns

=========================================================================


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "clk_contrl.v"
Module <clk_contrl> compiled
Compiling verilog file "front.v"
Module <front> compiled
Compiling verilog file "a_task.v"
Module <a_task> compiled
Compiling verilog file "b_task.v"
ERROR:HDLCompilers:120 - "b_task.v" line 29 Illegal redeclaration of input 'rdy_b' as a reg
ERROR:HDLCompilers:28 - "b_task.v" line 31 'rst' has not been declared
ERROR:HDLCompilers:28 - "b_task.v" line 33 'rst' has not been declared
Module <b_task> compiled
Compiling verilog file "back.v"
Module <back> compiled
Compiling verilog file "pingpang.v"
Module <pingpang> compiled
Analysis of file <"pingpang.prj"> failed.
--> 

Total memory usage is 77136 kilobytes

Number of errors   :    3 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "clk_contrl.v"
Module <clk_contrl> compiled
Compiling verilog file "front.v"
Module <front> compiled
Compiling verilog file "a_task.v"
Module <a_task> compiled
Compiling verilog file "b_task.v"
ERROR:HDLCompilers:120 - "b_task.v" line 30 Illegal redeclaration of input 'rdy_b' as a reg
Module <b_task> compiled
Compiling verilog file "back.v"
Module <back> compiled
Compiling verilog file "pingpang.v"
Module <pingpang> compiled
Analysis of file <"pingpang.prj"> failed.
--> 

Total memory usage is 77136 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "clk_contrl.v"
Module <clk_contrl> compiled
Compiling verilog file "front.v"
Module <front> compiled
Compiling verilog file "a_task.v"
Module <a_task> compiled
Compiling verilog file "b_task.v"
ERROR:HDLCompilers:120 - "b_task.v" line 30 Illegal redeclaration of input 'rdy_b' as a reg
Module <b_task> compiled
Compiling verilog file "back.v"
Module <back> compiled
Compiling verilog file "pingpang.v"
Module <pingpang> compiled
Analysis of file <"pingpang.prj"> failed.
--> 

Total memory usage is 77136 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "b_task.v"
ERROR:HDLCompilers:120 - "b_task.v" line 30 Illegal redeclaration of input 'rdy_b' as a reg
Module <b_task> compiled
Analysis of file <"b_task.prj"> failed.
--> 

Total memory usage is 77136 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================