📄 __projnav.log
字号:
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "front.v"ERROR:HDLCompilers:26 - "front.v" line 57 expecting 'end', found '1'ERROR:HDLCompilers:26 - "front.v" line 65 expecting 'end', found 'endcase'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'endcase', found 'if'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'end', found '('ERROR:HDLCompilers:26 - "front.v" line 66 unexpected token: 'rdy_a'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'end', found '1'ERROR:HDLCompilers:26 - "front.v" line 66 unexpected token: '<='Module <front> compiledERROR:HDLCompilers:26 - "front.v" line 66 expecting 'endmodule', found '0'Analysis of file <"front.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "front.v"ERROR:HDLCompilers:26 - "front.v" line 57 expecting 'end', found '1'ERROR:HDLCompilers:26 - "front.v" line 65 expecting 'end', found 'endcase'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'endcase', found 'if'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'end', found '('ERROR:HDLCompilers:26 - "front.v" line 66 unexpected token: 'rdy_a'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'end', found '1'ERROR:HDLCompilers:26 - "front.v" line 66 unexpected token: '<='Module <front> compiledERROR:HDLCompilers:26 - "front.v" line 66 expecting 'endmodule', found '0'Analysis of file <"front.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "front.v"ERROR:HDLCompilers:26 - "front.v" line 57 expecting 'end', found '1'ERROR:HDLCompilers:26 - "front.v" line 65 expecting 'end', found 'endcase'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'endcase', found 'if'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'end', found '('ERROR:HDLCompilers:26 - "front.v" line 66 unexpected token: 'rdy_a'ERROR:HDLCompilers:26 - "front.v" line 66 expecting 'end', found '1'ERROR:HDLCompilers:26 - "front.v" line 66 unexpected token: '<='Module <front> compiledERROR:HDLCompilers:26 - "front.v" line 66 expecting 'endmodule', found '0'Analysis of file <"front.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "front.v"Module <front> compiledNo errors in compilationAnalysis of file <"front.prj"> succeeded.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "front.v"Module <front> compiledNo errors in compilationAnalysis of file <"front.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <front>.Module <front> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <front>. Related source file is "front.v".WARNING:Xst:1306 - Output <b> is never assigned. Found 16-bit register for signal <a>. Found 1-bit register for signal <rdy_a>. Found 1-bit register for signal <rdy_b>. Found 1-bit register for signal <state>. Summary: inferred 19 D-type flip-flop(s).Unit <front> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 3 16-bit register : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <front> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/LijunYang_software/xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block front, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4 Number of Slices: 11 out of 3584 0% Number of Slice Flip Flops: 19 out of 7168 0% Number of 4 input LUTs: 4 out of 7168 0% Number of bonded IOBs: 53 out of 141 37% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_5m | BUFGP | 19 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 3.776ns (Maximum Frequency: 264.830MHz) Minimum input arrival time before clock: 4.467ns Maximum output required time after clock: 7.271ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledNo errors in compilationAnalysis of file <"clk_contrl.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <clk_contrl>.Module <clk_contrl> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clk_contrl>. Related source file is "clk_contrl.v". Found 1-bit register for signal <clk_2_5m>. Summary: inferred 1 D-type flip-flop(s).Unit <clk_contrl> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 1-bit register : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clk_contrl> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/LijunYang_software/xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clk_contrl, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4 Number of Slices: 1 out of 3584 0% Number of Slice Flip Flops: 1 out of 7168 0% Number of bonded IOBs: 3 out of 141 2% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_5m | BUFGP | 1 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 3.152ns (Maximum Frequency: 317.259MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 7.241ns Maximum combinational path delay: No path found=========================================================================
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -