b_task.v

实现乒乓缓存

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:28:00 12/26/07
// Design Name:    
// Module Name:    b_task
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module b_task(clk_2_5m,rst, nd_b, indata_b, out_b, rdy_b);
    input clk_2_5m;
	 input rst;
    input nd_b;
    input [15:0] indata_b;
    output [15:0] out_b;
    output rdy_b;

	 reg [15:0] out_b;
	 reg rdy_b;
	 
	 always @(posedge rst or posedge clk_2_5m)
	 begin
	  if(rst)
	     begin
		  rdy_b<=0;
		  end
	  else if(nd_b)
	     begin
		  out_b<=~indata_b;
		  rdy_b<=1;
		  end
	  else
	     if(rdy_b==1)rdy_b<=0;
	 end

endmodule