clk_contrl.v

来自「实现乒乓缓存」· Verilog 代码 · 共 45 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:36:54 12/26/07
// Design Name:    
// Module Name:    clk_contrl
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module clk_contrl(clk_5m, rst, clk_2_5m,clk_2_5m_inv);
    input clk_5m;
    input rst;
    output clk_2_5m;
	 output clk_2_5m_inv;
    
	 reg clk_2_5m;
	 reg clk_2_5m_inv;	 

	 always @(posedge rst or posedge clk_5m)
	 begin
	  if(rst)
	    begin
	    clk_2_5m<=0;
		 clk_2_5m_inv<=1;
		 end
	  else
	    begin
		 clk_2_5m<=~clk_2_5m;
		 clk_2_5m_inv<=~clk_2_5m_inv;
		 end
	 end

endmodule