pingpang.v

实现乒乓缓存

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:40:47 12/26/07
// Design Name:    
// Module Name:    pingpang
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module pingpang(clk_5m, rst, nd, indata, out, rdy);
    input clk_5m;
    input rst;
    input nd;
    input [15:0] indata;
    output [15:0] out;
    output rdy;

	 wire [15:0]  a;
	 wire [15:0]  b;
	 wire [15:0] out_a;
	 wire [15:0] out_b;
	 wire clk_2_5m,clk_2_5m_inv;
	 wire rdy_a,rdy_b,rdy_a_1,rdy_b_1;

	 clk_contrl clk_contrl_1(clk_5m, rst, clk_2_5m,clk_2_5m_inv);
	 front front_1(clk_5m,rst, nd, indata, a, b, rdy_a, rdy_b);
	 a_task a_task_1(clk_2_5m,rst, rdy_a, a, out_a, rdy_a_1);
	 b_task b_task_1(clk_2_5m_inv, rst,rdy_b, b, out_b, rdy_b_1);
	 back back_1(clk_5m,rst, rdy_a_1, rdy_b_1, out_a, out_b, out, rdy);

endmodule